Publications
OUR RESEARCH
Scientific Publications
Here you can find the comprehensive list of publications from the members of the Research Center on Computer Vision and eXtended Reality (xRAI).
Use the tag cloud to filter papers based on specific research topics, or use the menus to filter by year, type of publication, or authors.
For each paper, you have the option to view additional details such as the Abstract, Links, and BibTex record.
Research is formalized curiosity. It is poking and prying with a purpose
Zora Neale Hurston
2026
Pappalardo, Salvatore; Barone, Salvatore; Deveautour, Bastien; Ruospo, Annachiara; Sanchez, Ernesto; Traiola, Marcello; Bosio, Alberto
Analyzing the impact of functional approximation on the resilience of Deep Neural Networks Journal Article
In: Microprocessors and Microsystems, vol. 122, pp. 105259, 2026, ISSN: 0141-9331.
Abstract | Links | BibTeX | Tags:
@article{pappalardo_analyzing_2026,
title = {Analyzing the impact of functional approximation on the resilience of Deep Neural Networks},
author = {Salvatore Pappalardo and Salvatore Barone and Bastien Deveautour and Annachiara Ruospo and Ernesto Sanchez and Marcello Traiola and Alberto Bosio},
url = {https://www.sciencedirect.com/science/article/pii/S0141933126000165},
doi = {10.1016/j.micpro.2026.105259},
issn = {0141-9331},
year = {2026},
date = {2026-06-01},
urldate = {2026-03-06},
journal = {Microprocessors and Microsystems},
volume = {122},
pages = {105259},
abstract = {This paper investigates the use of Approximate Computing (AxC), specifically functional approximation, to enhance the resilience of Deep Neural Networks (DNNs) against hardware faults in various applications, including safety-critical systems such as autonomous vehicles. As deploying DNNs requires balancing performance, energy efficiency, and reliability, traditional methods often achieve reliability through redundancy, which can increase area, power consumption, and latency. Our work shows preliminary results that leveraging approximate multipliers can, under some conditions, lead to energy reductions without compromising DNN resilience, under the right conditions. We evaluate the impact of approximation on DNN performance and robustness, exploring the interplay between energy efficiency and fault tolerance. Through comprehensive benchmarking, we highlight the potential of AxC to enable more efficient and reliable DNN implementations, paving the way for advanced applications in real-time and edge computing environments. Results obtained on four different DNNs show that it is possible to achieve up to a 3× reduction in power consumption without any negative impact on resilience.},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
This paper investigates the use of Approximate Computing (AxC), specifically functional approximation, to enhance the resilience of Deep Neural Networks (DNNs) against hardware faults in various applications, including safety-critical systems such as autonomous vehicles. As deploying DNNs requires balancing performance, energy efficiency, and reliability, traditional methods often achieve reliability through redundancy, which can increase area, power consumption, and latency. Our work shows preliminary results that leveraging approximate multipliers can, under some conditions, lead to energy reductions without compromising DNN resilience, under the right conditions. We evaluate the impact of approximation on DNN performance and robustness, exploring the interplay between energy efficiency and fault tolerance. Through comprehensive benchmarking, we highlight the potential of AxC to enable more efficient and reliable DNN implementations, paving the way for advanced applications in real-time and edge computing environments. Results obtained on four different DNNs show that it is possible to achieve up to a 3× reduction in power consumption without any negative impact on resilience.
Barbareschi, Mario; Barone, Salvatore; Bosio, Alberto; Emmanuele, Antonio
Reliability analysis of hardware accelerators for decision tree-based classifier systems Journal Article
In: Future Generation Computer Systems, pp. 108378, 2026, ISSN: 0167-739X.
Abstract | Links | BibTeX | Tags:
@article{barbareschi_reliability_2026,
title = {Reliability analysis of hardware accelerators for decision tree-based classifier systems},
author = {Mario Barbareschi and Salvatore Barone and Alberto Bosio and Antonio Emmanuele},
url = {https://www.sciencedirect.com/science/article/pii/S0167739X26000129},
doi = {10.1016/j.future.2026.108378},
issn = {0167-739X},
year = {2026},
date = {2026-01-01},
urldate = {2026-01-21},
journal = {Future Generation Computer Systems},
pages = {108378},
abstract = {The increasing adoption of AI models has driven applications toward the use of hardware accelerators to meet high computational demands and strict performance requirements. Beyond consideration of performance and energy efficiency, explainability and reliability have emerged as pivotal requirements, particularly for critical applications such as automotive, medical, and aerospace systems. Among the various AI models, Decision Tree Ensembles (DTEs) are particularly notable for their high accuracy and explainability. Moreover, they are particularly well-suited for hardware implementations, enabling high-performance and improved energy efficiency. However, a frequently overlooked aspect of DTEs is their reliability in the presence of hardware malfunctions. While DTEs are generally regarded as robust by design, due to their redundancy and voting mechanisms, hardware faults can still have catastrophic consequences. To address this gap, we present an in-depth reliability analysis of two types of DTE hardware accelerators: classical and approximate implementations. Specifically, we conduct a comprehensive fault injection campaign, varying the number of trees involved in the classification task, the approximation technique used, and the tolerated accuracy loss, while evaluating several benchmark datasets. The results of this study demonstrate that approximation techniques have to be carefully designed, as they can significantly impact resilience. However, techniques that target the representation of features and thresholds appear to be better suited for fault tolerance.},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
The increasing adoption of AI models has driven applications toward the use of hardware accelerators to meet high computational demands and strict performance requirements. Beyond consideration of performance and energy efficiency, explainability and reliability have emerged as pivotal requirements, particularly for critical applications such as automotive, medical, and aerospace systems. Among the various AI models, Decision Tree Ensembles (DTEs) are particularly notable for their high accuracy and explainability. Moreover, they are particularly well-suited for hardware implementations, enabling high-performance and improved energy efficiency. However, a frequently overlooked aspect of DTEs is their reliability in the presence of hardware malfunctions. While DTEs are generally regarded as robust by design, due to their redundancy and voting mechanisms, hardware faults can still have catastrophic consequences. To address this gap, we present an in-depth reliability analysis of two types of DTE hardware accelerators: classical and approximate implementations. Specifically, we conduct a comprehensive fault injection campaign, varying the number of trees involved in the classification task, the approximation technique used, and the tolerated accuracy loss, while evaluating several benchmark datasets. The results of this study demonstrate that approximation techniques have to be carefully designed, as they can significantly impact resilience. However, techniques that target the representation of features and thresholds appear to be better suited for fault tolerance.
2025
Barbareschi, Mario; Barone, Salvatore; Mazzocca, Nicola; Moriconi, Alberto
Designing Energy-Efficient Approximate Circuits for the FPGA Technology Proceedings Article
In: Proceedings of the 28th Euromicro Conference on Digital System Design (DSD), Salerno, 2025.
@inproceedings{barbareschi_designing_2025,
title = {Designing Energy-Efficient Approximate Circuits for the FPGA Technology},
author = {Mario Barbareschi and Salvatore Barone and Nicola Mazzocca and Alberto Moriconi},
year = {2025},
date = {2025-01-01},
booktitle = {Proceedings of the 28th Euromicro Conference on Digital System Design (DSD)},
address = {Salerno},
abstract = {A significant number of contributions focusing on approximation techniques for Application Specific Integrated Circuits (ASIC) has become part of the scientific literature. Conversely, Field Programmable Gate Arrays (FPGAs) are often overlooked, despite their increasing spread. ASIC-based techniques are, however, often unsuitable when it comes to FPGA, providing little or no advantages at all, due to the inherent differences in the two target technologies. Most of the FPGA-based approximation techniques being recently proposed either rely on manual approximation, or are too tightly coupled with a particular FPGA fabric, making them ineffective or even inapplicable to other devices. Furthermore, they rely on machine-learning based predictors to drive the Design Space Exploration (DSE), that, given the high fidelity required, are usually burdensome to achieve, or even unfeasible when little or no training data is available. In this paper, we discuss a fabricand workload-independent approach to design power-optimized approximate circuits for FPGA. We exploit the existing bond between Look-Up Table (LUT)-mapping in FPGA synthesis and cut-enumeration in And-Inverter graph representation of digital circuits, and we resort to an analytical model to estimate the power consumption during the DSE, avoiding costly synthesis as well as machine-learning based predictors for hardware resources during the DSE. Several benchmark circuits are considered for evaluation purposes, and the significant savings achieved allow us to claim our approach is suitable for addressing approximate circuit design while targeting the FPGA.},
keywords = {},
pubstate = {published},
tppubtype = {inproceedings}
}
A significant number of contributions focusing on approximation techniques for Application Specific Integrated Circuits (ASIC) has become part of the scientific literature. Conversely, Field Programmable Gate Arrays (FPGAs) are often overlooked, despite their increasing spread. ASIC-based techniques are, however, often unsuitable when it comes to FPGA, providing little or no advantages at all, due to the inherent differences in the two target technologies. Most of the FPGA-based approximation techniques being recently proposed either rely on manual approximation, or are too tightly coupled with a particular FPGA fabric, making them ineffective or even inapplicable to other devices. Furthermore, they rely on machine-learning based predictors to drive the Design Space Exploration (DSE), that, given the high fidelity required, are usually burdensome to achieve, or even unfeasible when little or no training data is available. In this paper, we discuss a fabricand workload-independent approach to design power-optimized approximate circuits for FPGA. We exploit the existing bond between Look-Up Table (LUT)-mapping in FPGA synthesis and cut-enumeration in And-Inverter graph representation of digital circuits, and we resort to an analytical model to estimate the power consumption during the DSE, avoiding costly synthesis as well as machine-learning based predictors for hardware resources during the DSE. Several benchmark circuits are considered for evaluation purposes, and the significant savings achieved allow us to claim our approach is suitable for addressing approximate circuit design while targeting the FPGA.
Barbareschi, Mario; Barone, Salvatore; Casola, Valentina; Torca, Salvatore Della
Error Resiliency and Adversarial Robustness in Convolutional Neural Networks: An Empirical Analysis Proceedings Article
In: Rey, Gaëtan; Tigli, Jean-Yves; Franquet, Erwin (Ed.): Internet of Things, pp. 149–160, Springer Nature Switzerland, Cham, 2025, ISBN: 978-3-031-81900-1.
Abstract | Links | BibTeX | Tags:
@inproceedings{barbareschi_error_2025,
title = {Error Resiliency and Adversarial Robustness in Convolutional Neural Networks: An Empirical Analysis},
author = {Mario Barbareschi and Salvatore Barone and Valentina Casola and Salvatore Della Torca},
editor = {Gaëtan Rey and Jean-Yves Tigli and Erwin Franquet},
url = {https://link.springer.com/chapter/10.1007/978-3-031-81900-1_9},
doi = {10.1007/978-3-031-81900-1_9},
isbn = {978-3-031-81900-1},
year = {2025},
date = {2025-01-01},
booktitle = {Internet of Things},
pages = {149–160},
publisher = {Springer Nature Switzerland},
address = {Cham},
abstract = {The increasing pervasiveness of Artificial Intelligence (AI), and Convolutional Neural Networks (CNNs) in edge-computing and Internet of Things applications pose several challenges, including the hunger for computational and power resources of predictive models, and their robustness w.r.t. security threats, e.g., adversarial attacks. As for the former, the approximate computing emerged as one of the most promising solutions to lower the computational effort of AI, since the output of approximate application is usually barely distinguishable from the exact one. Nevertheless, alterations to predictive models through approximation may actually jeopardize inner characteristics of CNNs, such as their adversarial robustness, that is their ability to discern legitimate inputs from systematically crafted malicious ones.},
keywords = {},
pubstate = {published},
tppubtype = {inproceedings}
}
The increasing pervasiveness of Artificial Intelligence (AI), and Convolutional Neural Networks (CNNs) in edge-computing and Internet of Things applications pose several challenges, including the hunger for computational and power resources of predictive models, and their robustness w.r.t. security threats, e.g., adversarial attacks. As for the former, the approximate computing emerged as one of the most promising solutions to lower the computational effort of AI, since the output of approximate application is usually barely distinguishable from the exact one. Nevertheless, alterations to predictive models through approximation may actually jeopardize inner characteristics of CNNs, such as their adversarial robustness, that is their ability to discern legitimate inputs from systematically crafted malicious ones.
Barbareschi, Mario; Barone, Salvatore; Bosio, Alberto; Deveautour, Bastien; Piri, Ali; Traiola, Marcello
Automatic generation of input-aware approximate arithmetic circuits Proceedings Article
In: 2025 IEEE 28th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), pp. 139–144, IEEE, 2025.
@inproceedings{barbareschi_automatic_2025,
title = {Automatic generation of input-aware approximate arithmetic circuits},
author = {Mario Barbareschi and Salvatore Barone and Alberto Bosio and Bastien Deveautour and Ali Piri and Marcello Traiola},
url = {https://ieeexplore.ieee.org/abstract/document/11006680/},
year = {2025},
date = {2025-01-01},
urldate = {2025-09-16},
booktitle = {2025 IEEE 28th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)},
pages = {139–144},
publisher = {IEEE},
keywords = {},
pubstate = {published},
tppubtype = {inproceedings}
}
Bellarmino, Nicolò; Barone, Salvatore; Pappalardo, Salvatore; Bosio, Alberto; Cantoro, Riccardo
OpRA: Optimizing Resiliency Assessment for Deep Neural Networks Journal Article
In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp. 1–1, 2025, ISSN: 1937-4151.
Abstract | Links | BibTeX | Tags:
@article{bellarmino_opra_2025,
title = {OpRA: Optimizing Resiliency Assessment for Deep Neural Networks},
author = {Nicolò Bellarmino and Salvatore Barone and Salvatore Pappalardo and Alberto Bosio and Riccardo Cantoro},
url = {https://ieeexplore.ieee.org/document/11164517},
doi = {10.1109/TCAD.2025.3610062},
issn = {1937-4151},
year = {2025},
date = {2025-01-01},
urldate = {2025-09-16},
journal = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},
pages = {1–1},
abstract = {Deep Neural Networks (DNNs) and especially Convolutional Neural Networks (CNNs) are increasingly deployed in safety-critical domains, where rigorous reliability assessment is essential. Fault Injection (FI) remains a widely adopted technique to evaluate DNN robustness under hardware faults. However, the high computational cost of FI campaigns limits their scalability and practical adoption. These campaigns traditionally rely on three components: the DNN model, a fault list, and an input stimulus set. While fault selection strategies have been extensively studied, the impact of input stimulus selection remains largely underexplored. This work addresses this gap by investigating the role of input stimuli in activating critical faults during FI-based reliability evaluation. We propose a strategy to prioritize inputs that are more likely to expose fault-induced vulnerabilities, guided by uncertainty-based metrics. Our methodology is validated across two fault models: memory-level bit flips and stuck-at faults in a systolic array accelerator. Results show that uncertainty-ranked inputs significantly increase fault activation and detection efficiency, enabling more focused and cost-effective reliability analysis.},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
Deep Neural Networks (DNNs) and especially Convolutional Neural Networks (CNNs) are increasingly deployed in safety-critical domains, where rigorous reliability assessment is essential. Fault Injection (FI) remains a widely adopted technique to evaluate DNN robustness under hardware faults. However, the high computational cost of FI campaigns limits their scalability and practical adoption. These campaigns traditionally rely on three components: the DNN model, a fault list, and an input stimulus set. While fault selection strategies have been extensively studied, the impact of input stimulus selection remains largely underexplored. This work addresses this gap by investigating the role of input stimuli in activating critical faults during FI-based reliability evaluation. We propose a strategy to prioritize inputs that are more likely to expose fault-induced vulnerabilities, guided by uncertainty-based metrics. Our methodology is validated across two fault models: memory-level bit flips and stuck-at faults in a systolic array accelerator. Results show that uncertainty-ranked inputs significantly increase fault activation and detection efficiency, enabling more focused and cost-effective reliability analysis.
Barbareschi, Mario; Barone, Salvatore
Investigating the Resilience Source of Classification Systems for Approximate Computing Techniques Journal Article
In: IEEE Transactions on Emerging Topics in Computing, pp. 12, 2025, ISSN: 2168-6750.
Abstract | Links | BibTeX | Tags: Artificial Intelligence, Classification systems, Neural networks, Tree Ensemble
@article{barbareschi_investigating_2025,
title = {Investigating the Resilience Source of Classification Systems for Approximate Computing Techniques},
author = {Mario Barbareschi and Salvatore Barone},
url = {https://ieeexplore.ieee.org/document/10542568},
doi = {10.1109/TETC.2024.3403757},
issn = {2168-6750},
year = {2025},
date = {2025-01-01},
journal = {IEEE Transactions on Emerging Topics in Computing},
pages = {12},
abstract = {During the last decade, classification systems (CSs) received significant research attention, with new learning algorithms achieving high accuracy in various applications. However, their resource-intensive nature, in terms of hardware and computation time, poses new design challenges.
CSs exhibit inherent error resilience, due to redundancy of training sets, and self-healing properties, making them suitable for Approximate Computing (AxC).
AxC enables efficient computation by using reduced precision or approximate values, leading to energy, time, and silicon area savings.
Exploiting AxC involves estimating the introduced error for each approximate variant found during a Design-Space Exploration (DSE). This estimation has to be both rapid and meaningful, considering a substantial number of test samples, which are utterly conflicting demands.
In this paper, we investigate on sources of error resiliency of CSs, and we propose a technique to haste the DSE that reduces the computational time for error estimation by systematically reducing the test set. In particular, we cherry-pick samples that are likely to be more sensitive to approximation and perform accuracy-loss estimation just by exploiting such a sample subset.
In order to demonstrate its efficacy, we integrate our technique into two different approaches for generating approximate CSs, showing an average speed-up up to approx18.},
keywords = {Artificial Intelligence, Classification systems, Neural networks, Tree Ensemble},
pubstate = {published},
tppubtype = {article}
}
During the last decade, classification systems (CSs) received significant research attention, with new learning algorithms achieving high accuracy in various applications. However, their resource-intensive nature, in terms of hardware and computation time, poses new design challenges.
CSs exhibit inherent error resilience, due to redundancy of training sets, and self-healing properties, making them suitable for Approximate Computing (AxC).
AxC enables efficient computation by using reduced precision or approximate values, leading to energy, time, and silicon area savings.
Exploiting AxC involves estimating the introduced error for each approximate variant found during a Design-Space Exploration (DSE). This estimation has to be both rapid and meaningful, considering a substantial number of test samples, which are utterly conflicting demands.
In this paper, we investigate on sources of error resiliency of CSs, and we propose a technique to haste the DSE that reduces the computational time for error estimation by systematically reducing the test set. In particular, we cherry-pick samples that are likely to be more sensitive to approximation and perform accuracy-loss estimation just by exploiting such a sample subset.
In order to demonstrate its efficacy, we integrate our technique into two different approaches for generating approximate CSs, showing an average speed-up up to approx18.
CSs exhibit inherent error resilience, due to redundancy of training sets, and self-healing properties, making them suitable for Approximate Computing (AxC).
AxC enables efficient computation by using reduced precision or approximate values, leading to energy, time, and silicon area savings.
Exploiting AxC involves estimating the introduced error for each approximate variant found during a Design-Space Exploration (DSE). This estimation has to be both rapid and meaningful, considering a substantial number of test samples, which are utterly conflicting demands.
In this paper, we investigate on sources of error resiliency of CSs, and we propose a technique to haste the DSE that reduces the computational time for error estimation by systematically reducing the test set. In particular, we cherry-pick samples that are likely to be more sensitive to approximation and perform accuracy-loss estimation just by exploiting such a sample subset.
In order to demonstrate its efficacy, we integrate our technique into two different approaches for generating approximate CSs, showing an average speed-up up to approx18.
2024
Barbareschi, Mario; Barone, Salvatore; Mazzocca, Nicola; Moriconi, Alberto
FPGA approximate logic synthesis through catalog-based AIG-rewriting technique Journal Article
In: Journal of Systems Architecture, vol. 150, pp. 103112, 2024, ISSN: 1383-7621.
Abstract | Links | BibTeX | Tags:
@article{barbareschiFPGAApproximateLogic2024,
title = {FPGA approximate logic synthesis through catalog-based AIG-rewriting technique},
author = {Mario Barbareschi and Salvatore Barone and Nicola Mazzocca and Alberto Moriconi},
url = {https://www.sciencedirect.com/science/article/pii/S1383762124000493},
doi = {10.1016/j.sysarc.2024.103112},
issn = {1383-7621},
year = {2024},
date = {2024-05-01},
urldate = {2024-07-11},
journal = {Journal of Systems Architecture},
volume = {150},
pages = {103112},
abstract = {Due to their run-time reconfigurability, short time-to-market, and lower prototype costs, FPGAs have become increasingly popular since their introduction. They found use in a wide variety of applications, including high-performance computing. However, when compared to ASICs, FPGAs offer lower performance, and they are power-hungry devices with low energy-efficiency. The emergence of Approximate Computing (AxC) represents a significant advancement in terms of enabling technology when applied to FPGA-based computing platforms. It has been effectively exploited in several application fields, achieving significant savings in energy and latency through a selective degradation of the output quality. Nevertheless, a generalized and systematic methodology for FPGA-based circuit design is still lacking. Indeed, most of the methods target ASIC-based systems, and, consequently, they offer minimal advantages or even an increase in resources when synthesized for FPGAs due to the architectural differences between the technologies. In this paper, we attempt to address this shortcoming by introducing our method for designing combinational logic circuits. It is based on and-inverter graph rewriting and multi-objective optimization, aiming for optimal trade-offs between quality of results and hardware overhead. Extensive experimental campaigns empirically prove that both generic logic and arithmetic circuits benefit from this approach.},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
Due to their run-time reconfigurability, short time-to-market, and lower prototype costs, FPGAs have become increasingly popular since their introduction. They found use in a wide variety of applications, including high-performance computing. However, when compared to ASICs, FPGAs offer lower performance, and they are power-hungry devices with low energy-efficiency. The emergence of Approximate Computing (AxC) represents a significant advancement in terms of enabling technology when applied to FPGA-based computing platforms. It has been effectively exploited in several application fields, achieving significant savings in energy and latency through a selective degradation of the output quality. Nevertheless, a generalized and systematic methodology for FPGA-based circuit design is still lacking. Indeed, most of the methods target ASIC-based systems, and, consequently, they offer minimal advantages or even an increase in resources when synthesized for FPGAs due to the architectural differences between the technologies. In this paper, we attempt to address this shortcoming by introducing our method for designing combinational logic circuits. It is based on and-inverter graph rewriting and multi-objective optimization, aiming for optimal trade-offs between quality of results and hardware overhead. Extensive experimental campaigns empirically prove that both generic logic and arithmetic circuits benefit from this approach.
Barbareschi, Mario; Barone, Salvatore; Mazzocca, Nicola; Moriconi, Alberto
FPGA approximate logic synthesis through catalog-based AIG-rewriting technique Journal Article
In: Journal of Systems Architecture, vol. 150, pp. 103112, 2024, ISSN: 1383-7621.
Abstract | Links | BibTeX | Tags:
@article{barbareschi_fpga_2024,
title = {FPGA approximate logic synthesis through catalog-based AIG-rewriting technique},
author = {Mario Barbareschi and Salvatore Barone and Nicola Mazzocca and Alberto Moriconi},
url = {https://www.sciencedirect.com/science/article/pii/S1383762124000493},
doi = {10.1016/j.sysarc.2024.103112},
issn = {1383-7621},
year = {2024},
date = {2024-05-01},
urldate = {2024-07-11},
journal = {Journal of Systems Architecture},
volume = {150},
pages = {103112},
abstract = {Due to their run-time reconfigurability, short time-to-market, and lower prototype costs, FPGAs have become increasingly popular since their introduction. They found use in a wide variety of applications, including high-performance computing. However, when compared to ASICs, FPGAs offer lower performance, and they are power-hungry devices with low energy-efficiency. The emergence of Approximate Computing (AxC) represents a significant advancement in terms of enabling technology when applied to FPGA-based computing platforms. It has been effectively exploited in several application fields, achieving significant savings in energy and latency through a selective degradation of the output quality. Nevertheless, a generalized and systematic methodology for FPGA-based circuit design is still lacking. Indeed, most of the methods target ASIC-based systems, and, consequently, they offer minimal advantages or even an increase in resources when synthesized for FPGAs due to the architectural differences between the technologies. In this paper, we attempt to address this shortcoming by introducing our method for designing combinational logic circuits. It is based on and-inverter graph rewriting and multi-objective optimization, aiming for optimal trade-offs between quality of results and hardware overhead. Extensive experimental campaigns empirically prove that both generic logic and arithmetic circuits benefit from this approach.},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
Due to their run-time reconfigurability, short time-to-market, and lower prototype costs, FPGAs have become increasingly popular since their introduction. They found use in a wide variety of applications, including high-performance computing. However, when compared to ASICs, FPGAs offer lower performance, and they are power-hungry devices with low energy-efficiency. The emergence of Approximate Computing (AxC) represents a significant advancement in terms of enabling technology when applied to FPGA-based computing platforms. It has been effectively exploited in several application fields, achieving significant savings in energy and latency through a selective degradation of the output quality. Nevertheless, a generalized and systematic methodology for FPGA-based circuit design is still lacking. Indeed, most of the methods target ASIC-based systems, and, consequently, they offer minimal advantages or even an increase in resources when synthesized for FPGAs due to the architectural differences between the technologies. In this paper, we attempt to address this shortcoming by introducing our method for designing combinational logic circuits. It is based on and-inverter graph rewriting and multi-objective optimization, aiming for optimal trade-offs between quality of results and hardware overhead. Extensive experimental campaigns empirically prove that both generic logic and arithmetic circuits benefit from this approach.
Barbareschi, Mario; Barone, Salvatore
Investigating the Resilience Source of Classification Systems for Approximate Computing Techniques Journal Article
In: IEEE Transactions on Emerging Topics in Computing, pp. 12, 2024, ISSN: 2168-6750.
Abstract | Links | BibTeX | Tags: Artificial Intelligence, Classification systems, Neural networks, Tree Ensemble
@article{barbareschi_investigating_2024,
title = {Investigating the Resilience Source of Classification Systems for Approximate Computing Techniques},
author = {Mario Barbareschi and Salvatore Barone},
url = {https://ieeexplore.ieee.org/document/10542568},
doi = {10.1109/TETC.2024.3403757},
issn = {2168-6750},
year = {2024},
date = {2024-01-01},
journal = {IEEE Transactions on Emerging Topics in Computing},
pages = {12},
abstract = {During the last decade, classification systems (CSs) received significant research attention, with new learning algorithms achieving high accuracy in various applications. However, their resource-intensive nature, in terms of hardware and computation time, poses new design challenges.
CSs exhibit inherent error resilience, due to redundancy of training sets, and self-healing properties, making them suitable for Approximate Computing (AxC).
AxC enables efficient computation by using reduced precision or approximate values, leading to energy, time, and silicon area savings.
Exploiting AxC involves estimating the introduced error for each approximate variant found during a Design-Space Exploration (DSE). This estimation has to be both rapid and meaningful, considering a substantial number of test samples, which are utterly conflicting demands.
In this paper, we investigate on sources of error resiliency of CSs, and we propose a technique to haste the DSE that reduces the computational time for error estimation by systematically reducing the test set. In particular, we cherry-pick samples that are likely to be more sensitive to approximation and perform accuracy-loss estimation just by exploiting such a sample subset.
In order to demonstrate its efficacy, we integrate our technique into two different approaches for generating approximate CSs, showing an average speed-up up to approx18.},
keywords = {Artificial Intelligence, Classification systems, Neural networks, Tree Ensemble},
pubstate = {published},
tppubtype = {article}
}
During the last decade, classification systems (CSs) received significant research attention, with new learning algorithms achieving high accuracy in various applications. However, their resource-intensive nature, in terms of hardware and computation time, poses new design challenges.
CSs exhibit inherent error resilience, due to redundancy of training sets, and self-healing properties, making them suitable for Approximate Computing (AxC).
AxC enables efficient computation by using reduced precision or approximate values, leading to energy, time, and silicon area savings.
Exploiting AxC involves estimating the introduced error for each approximate variant found during a Design-Space Exploration (DSE). This estimation has to be both rapid and meaningful, considering a substantial number of test samples, which are utterly conflicting demands.
In this paper, we investigate on sources of error resiliency of CSs, and we propose a technique to haste the DSE that reduces the computational time for error estimation by systematically reducing the test set. In particular, we cherry-pick samples that are likely to be more sensitive to approximation and perform accuracy-loss estimation just by exploiting such a sample subset.
In order to demonstrate its efficacy, we integrate our technique into two different approaches for generating approximate CSs, showing an average speed-up up to approx18.
CSs exhibit inherent error resilience, due to redundancy of training sets, and self-healing properties, making them suitable for Approximate Computing (AxC).
AxC enables efficient computation by using reduced precision or approximate values, leading to energy, time, and silicon area savings.
Exploiting AxC involves estimating the introduced error for each approximate variant found during a Design-Space Exploration (DSE). This estimation has to be both rapid and meaningful, considering a substantial number of test samples, which are utterly conflicting demands.
In this paper, we investigate on sources of error resiliency of CSs, and we propose a technique to haste the DSE that reduces the computational time for error estimation by systematically reducing the test set. In particular, we cherry-pick samples that are likely to be more sensitive to approximation and perform accuracy-loss estimation just by exploiting such a sample subset.
In order to demonstrate its efficacy, we integrate our technique into two different approaches for generating approximate CSs, showing an average speed-up up to approx18.
Barbareschi, Mario; Barone, Salvatore; Bosio, Alberto; Traiola, Marcello
Automatic Approximation of Computer Systems Through Multi-objective Optimization Book Section
In: Liu, Weiqiang; Han, Jie; Lombardi, Fabrizio (Ed.): Design and Applications of Emerging Computer Systems, pp. 383–420, Springer Nature Switzerland, Cham, 2024, ISBN: 978-3-031-42478-6, (tex.copyright: All rights reserved).
Abstract | Links | BibTeX | Tags: Computer science, Design-space Exploration, Digital, Hardware and Architecture, Industry and Space, Multi-objective optimization
@incollection{barbareschi_automatic_2024,
title = {Automatic Approximation of Computer Systems Through Multi-objective Optimization},
author = {Mario Barbareschi and Salvatore Barone and Alberto Bosio and Marcello Traiola},
editor = {Weiqiang Liu and Jie Han and Fabrizio Lombardi},
url = {https://doi.org/10.1007/978-3-031-42478-6_15},
doi = {10.1007/978-3-031-42478-6_15},
isbn = {978-3-031-42478-6},
year = {2024},
date = {2024-01-01},
urldate = {2024-01-17},
booktitle = {Design and Applications of Emerging Computer Systems},
pages = {383–420},
publisher = {Springer Nature Switzerland},
address = {Cham},
abstract = {In this chapter, we address the automatic approximation of computer systems through multi-objective optimization. Firstly, we present our automatic design methodology, i.e., how we model the approximate design space to be automatically explored. The exploration is achieved through multi-objective optimization to find good trade-offs between the system efficiency and accuracy. Then, we show how the methodology is applied to the systematic and application-independent design of generic combinational logic circuits, based on non-trivial local rewriting of and-inverter graphs (AIGs). Finally, to push forward the approximation limits, we showcase the design of approximate hardware accelerators for image processing and for common machine-learning-based classification models.},
note = {tex.copyright: All rights reserved},
keywords = {Computer science, Design-space Exploration, Digital, Hardware and Architecture, Industry and Space, Multi-objective optimization},
pubstate = {published},
tppubtype = {incollection}
}
In this chapter, we address the automatic approximation of computer systems through multi-objective optimization. Firstly, we present our automatic design methodology, i.e., how we model the approximate design space to be automatically explored. The exploration is achieved through multi-objective optimization to find good trade-offs between the system efficiency and accuracy. Then, we show how the methodology is applied to the systematic and application-independent design of generic combinational logic circuits, based on non-trivial local rewriting of and-inverter graphs (AIGs). Finally, to push forward the approximation limits, we showcase the design of approximate hardware accelerators for image processing and for common machine-learning-based classification models.
Barbareschi, Mario; Barone, Salvatore; Emmanuele, Antonio; Mazzocca, Nicola
Exploiting Functional Approximation on Decision-Tree based Multiple Classifier Systems Proceedings Article
In: Proceedingsof the IFIP/IEEE International Conference on Very Large Scale Integration (In Press), IFIP/IEEE, Tanger, Marocco, 2024.
@inproceedings{barbareschiExploitingFunctionalApproximation2024,
title = {Exploiting Functional Approximation on Decision-Tree based Multiple Classifier Systems},
author = {Mario Barbareschi and Salvatore Barone and Antonio Emmanuele and Nicola Mazzocca},
year = {2024},
date = {2024-01-01},
booktitle = {Proceedingsof the IFIP/IEEE International Conference on Very Large Scale Integration (In Press)},
publisher = {IFIP/IEEE},
address = {Tanger, Marocco},
abstract = {Multiple Classifier Systems (MCSs) have been increasingly designed to take advantage of hardware features, such as high parallelism and computational power, to guarantee higher throughput and lower latency.
Although the combination of multiple classifiers leads to high classification accuracy, the required area overhead makes the design of a hardware accelerator unfeasible, hindering the adoption of commercial configurable devices.
For this reason, in this paper, we exploit the Approximate Computing (AxC) design paradigm to automatically generate approximated hardware implementations of MCSs by trading hardware area overhead off for classification accuracy. In particular, we propose an algorithm that identifies the resiliency source of the model and uses it to introduce approximation with minimum accuracy loss. In order to prove the effectiveness of our solution, we performed numerous experiments on models of various sizes trained on different datasets. The results show that with negligible accuracy loss it is possible to significantly reduce the hardware requirements of a classifier.},
keywords = {},
pubstate = {published},
tppubtype = {inproceedings}
}
Multiple Classifier Systems (MCSs) have been increasingly designed to take advantage of hardware features, such as high parallelism and computational power, to guarantee higher throughput and lower latency.
Although the combination of multiple classifiers leads to high classification accuracy, the required area overhead makes the design of a hardware accelerator unfeasible, hindering the adoption of commercial configurable devices.
For this reason, in this paper, we exploit the Approximate Computing (AxC) design paradigm to automatically generate approximated hardware implementations of MCSs by trading hardware area overhead off for classification accuracy. In particular, we propose an algorithm that identifies the resiliency source of the model and uses it to introduce approximation with minimum accuracy loss. In order to prove the effectiveness of our solution, we performed numerous experiments on models of various sizes trained on different datasets. The results show that with negligible accuracy loss it is possible to significantly reduce the hardware requirements of a classifier.
Although the combination of multiple classifiers leads to high classification accuracy, the required area overhead makes the design of a hardware accelerator unfeasible, hindering the adoption of commercial configurable devices.
For this reason, in this paper, we exploit the Approximate Computing (AxC) design paradigm to automatically generate approximated hardware implementations of MCSs by trading hardware area overhead off for classification accuracy. In particular, we propose an algorithm that identifies the resiliency source of the model and uses it to introduce approximation with minimum accuracy loss. In order to prove the effectiveness of our solution, we performed numerous experiments on models of various sizes trained on different datasets. The results show that with negligible accuracy loss it is possible to significantly reduce the hardware requirements of a classifier.
Barbareschi, Mario; Barone, Salvatore; Casola, Valentina; Lombardi, Daniele
A comprehensive evaluation of interrupt measurement techniques for predictability in safety-critical systems Proceedings Article
In: Proceedings of the 19th International Conference on Availability, Reliability and Security (ARES 2024) (In press), Association for Computing Machinmery, Vienna, 2024, ISBN: 979-8-4007-1718-5.
Abstract | Links | BibTeX | Tags: Real-time systems
@inproceedings{barbareschiComprehensiveEvaluationInterrupt2024,
title = {A comprehensive evaluation of interrupt measurement techniques for predictability in safety-critical systems},
author = {Mario Barbareschi and Salvatore Barone and Valentina Casola and Daniele Lombardi},
doi = {10.1145/3664476.3670451},
isbn = {979-8-4007-1718-5},
year = {2024},
date = {2024-01-01},
booktitle = {Proceedings of the 19th International Conference on Availability, Reliability and Security (ARES 2024) (In press)},
publisher = {Association for Computing Machinmery},
address = {Vienna},
abstract = {In the last few decades, the increasing adoption of computer systems for monitoring and control applications has fostered growing attention to real-time behavior, i.e., the property that ensures predictable reaction times to external events.
In this perspective, performance of the interrupt management mechanisms are among the most relevant aspects to be considered.
Therefore, the service-latency of interrupts is one of the metrics considered while assessing the predictability of such systems.
To this purpose, there are different techniques to estimate it, including the use of on-board timers, oscilloscopes and logic analyzers, or even real-time tracers.
Each of these techniques, however, is affected by some degrees of inaccuracy, and choosing one over the other have pros and cons.
In this paper, we review methodologies for measuring interrupt-latency from the scientific literature and, for the first time, we define an analytical model that we exploit to figure out measurement errors committed. Finally, we prove the effectiveness of the model relying on measurements taken from Xilinx MPSoC devices and present a case study whose purpose is to validate the proposed model.},
keywords = {Real-time systems},
pubstate = {published},
tppubtype = {inproceedings}
}
In the last few decades, the increasing adoption of computer systems for monitoring and control applications has fostered growing attention to real-time behavior, i.e., the property that ensures predictable reaction times to external events.
In this perspective, performance of the interrupt management mechanisms are among the most relevant aspects to be considered.
Therefore, the service-latency of interrupts is one of the metrics considered while assessing the predictability of such systems.
To this purpose, there are different techniques to estimate it, including the use of on-board timers, oscilloscopes and logic analyzers, or even real-time tracers.
Each of these techniques, however, is affected by some degrees of inaccuracy, and choosing one over the other have pros and cons.
In this paper, we review methodologies for measuring interrupt-latency from the scientific literature and, for the first time, we define an analytical model that we exploit to figure out measurement errors committed. Finally, we prove the effectiveness of the model relying on measurements taken from Xilinx MPSoC devices and present a case study whose purpose is to validate the proposed model.
In this perspective, performance of the interrupt management mechanisms are among the most relevant aspects to be considered.
Therefore, the service-latency of interrupts is one of the metrics considered while assessing the predictability of such systems.
To this purpose, there are different techniques to estimate it, including the use of on-board timers, oscilloscopes and logic analyzers, or even real-time tracers.
Each of these techniques, however, is affected by some degrees of inaccuracy, and choosing one over the other have pros and cons.
In this paper, we review methodologies for measuring interrupt-latency from the scientific literature and, for the first time, we define an analytical model that we exploit to figure out measurement errors committed. Finally, we prove the effectiveness of the model relying on measurements taken from Xilinx MPSoC devices and present a case study whose purpose is to validate the proposed model.
Barone, Salvatore; Casola, Valentina; Torca, Salvatore Della
Ineffectiveness of Digital Transformations for Detecting Adversarial Attacks against Quantized and Approximate CNNs Proceedings Article
In: Proceedings of the 2024 IEEE International Conference on Cyber Security and Resilience (In press), pp. 6, London, UK, 2024.
@inproceedings{baroneIneffectivenessDigitalTransformations2024,
title = {Ineffectiveness of Digital Transformations for Detecting Adversarial Attacks against Quantized and Approximate CNNs},
author = {Salvatore Barone and Valentina Casola and Salvatore Della Torca},
year = {2024},
date = {2024-01-01},
booktitle = {Proceedings of the 2024 IEEE International Conference on Cyber Security and Resilience (In press)},
pages = {6},
address = {London, UK},
abstract = {Convolutional Neural Networks (CNNs) have achieved superhuman performance in computer vision tasks. However, these networks are becoming both increasingly complex and resource-intensive, and are susceptible to adversarial attacks.
On one hand, to counter complexity and resource-related limitations, various techniques such as Quantization and Approximate Computing (AxC) have been proposed to reduce the complexity and power consumption of CNNs, respectively.
On the other hand, various techniques have been proposed to craft more precise and stronger adversarial attacks, as well as new methodologies to defend against them.
Nevertheless, the relationship between the efficiency and security of CNNs is not adequately addressed.
Therefore, this article examines the potential for detecting adversarial attacks against CNNs through image transformation, in the context of quantized and approximate neural networks.
The experimental results indicate that image-transformation techniques are not effective in detecting adversarial samples against quantized and approximated CNNs, despite their success in detecting such samples against floating-point CNNs.},
keywords = {},
pubstate = {published},
tppubtype = {inproceedings}
}
Convolutional Neural Networks (CNNs) have achieved superhuman performance in computer vision tasks. However, these networks are becoming both increasingly complex and resource-intensive, and are susceptible to adversarial attacks.
On one hand, to counter complexity and resource-related limitations, various techniques such as Quantization and Approximate Computing (AxC) have been proposed to reduce the complexity and power consumption of CNNs, respectively.
On the other hand, various techniques have been proposed to craft more precise and stronger adversarial attacks, as well as new methodologies to defend against them.
Nevertheless, the relationship between the efficiency and security of CNNs is not adequately addressed.
Therefore, this article examines the potential for detecting adversarial attacks against CNNs through image transformation, in the context of quantized and approximate neural networks.
The experimental results indicate that image-transformation techniques are not effective in detecting adversarial samples against quantized and approximated CNNs, despite their success in detecting such samples against floating-point CNNs.
On one hand, to counter complexity and resource-related limitations, various techniques such as Quantization and Approximate Computing (AxC) have been proposed to reduce the complexity and power consumption of CNNs, respectively.
On the other hand, various techniques have been proposed to craft more precise and stronger adversarial attacks, as well as new methodologies to defend against them.
Nevertheless, the relationship between the efficiency and security of CNNs is not adequately addressed.
Therefore, this article examines the potential for detecting adversarial attacks against CNNs through image transformation, in the context of quantized and approximate neural networks.
The experimental results indicate that image-transformation techniques are not effective in detecting adversarial samples against quantized and approximated CNNs, despite their success in detecting such samples against floating-point CNNs.
Barbareschi, Mario; Barone, Salvatore; Casola, Valentina; Lombardi, Daniele
A comprehensive evaluation of interrupt measurement techniques for predictability in safety-critical systems Proceedings Article
In: Proceedings of the 19th International Conference on Availability, Reliability and Security (ARES 2024) (In press), Association for Computing Machinmery, Vienna, 2024, ISBN: 979-8-4007-1718-5.
Abstract | Links | BibTeX | Tags: Real-time systems
@inproceedings{barbareschi_comprehensive_2024,
title = {A comprehensive evaluation of interrupt measurement techniques for predictability in safety-critical systems},
author = {Mario Barbareschi and Salvatore Barone and Valentina Casola and Daniele Lombardi},
doi = {10.1145/3664476.3670451},
isbn = {979-8-4007-1718-5},
year = {2024},
date = {2024-01-01},
booktitle = {Proceedings of the 19th International Conference on Availability, Reliability and Security (ARES 2024) (In press)},
publisher = {Association for Computing Machinmery},
address = {Vienna},
abstract = {In the last few decades, the increasing adoption of computer systems for monitoring and control applications has fostered growing attention to real-time behavior, i.e., the property that ensures predictable reaction times to external events.
In this perspective, performance of the interrupt management mechanisms are among the most relevant aspects to be considered.
Therefore, the service-latency of interrupts is one of the metrics considered while assessing the predictability of such systems.
To this purpose, there are different techniques to estimate it, including the use of on-board timers, oscilloscopes and logic analyzers, or even real-time tracers.
Each of these techniques, however, is affected by some degrees of inaccuracy, and choosing one over the other have pros and cons.
In this paper, we review methodologies for measuring interrupt-latency from the scientific literature and, for the first time, we define an analytical model that we exploit to figure out measurement errors committed. Finally, we prove the effectiveness of the model relying on measurements taken from Xilinx MPSoC devices and present a case study whose purpose is to validate the proposed model.},
keywords = {Real-time systems},
pubstate = {published},
tppubtype = {inproceedings}
}
In the last few decades, the increasing adoption of computer systems for monitoring and control applications has fostered growing attention to real-time behavior, i.e., the property that ensures predictable reaction times to external events.
In this perspective, performance of the interrupt management mechanisms are among the most relevant aspects to be considered.
Therefore, the service-latency of interrupts is one of the metrics considered while assessing the predictability of such systems.
To this purpose, there are different techniques to estimate it, including the use of on-board timers, oscilloscopes and logic analyzers, or even real-time tracers.
Each of these techniques, however, is affected by some degrees of inaccuracy, and choosing one over the other have pros and cons.
In this paper, we review methodologies for measuring interrupt-latency from the scientific literature and, for the first time, we define an analytical model that we exploit to figure out measurement errors committed. Finally, we prove the effectiveness of the model relying on measurements taken from Xilinx MPSoC devices and present a case study whose purpose is to validate the proposed model.
In this perspective, performance of the interrupt management mechanisms are among the most relevant aspects to be considered.
Therefore, the service-latency of interrupts is one of the metrics considered while assessing the predictability of such systems.
To this purpose, there are different techniques to estimate it, including the use of on-board timers, oscilloscopes and logic analyzers, or even real-time tracers.
Each of these techniques, however, is affected by some degrees of inaccuracy, and choosing one over the other have pros and cons.
In this paper, we review methodologies for measuring interrupt-latency from the scientific literature and, for the first time, we define an analytical model that we exploit to figure out measurement errors committed. Finally, we prove the effectiveness of the model relying on measurements taken from Xilinx MPSoC devices and present a case study whose purpose is to validate the proposed model.
Barone, Salvatore; Casola, Valentina; Torca, Salvatore Della
Ineffectiveness of Digital Transformations for Detecting Adversarial Attacks against Quantized and Approximate CNNs Proceedings Article
In: Proceedings of the 2024 IEEE International Conference on Cyber Security and Resilience (In press), pp. 6, London, UK, 2024.
@inproceedings{barone_ineffectiveness_2024,
title = {Ineffectiveness of Digital Transformations for Detecting Adversarial Attacks against Quantized and Approximate CNNs},
author = {Salvatore Barone and Valentina Casola and Salvatore Della Torca},
year = {2024},
date = {2024-01-01},
booktitle = {Proceedings of the 2024 IEEE International Conference on Cyber Security and Resilience (In press)},
pages = {6},
address = {London, UK},
abstract = {Convolutional Neural Networks (CNNs) have achieved superhuman performance in computer vision tasks. However, these networks are becoming both increasingly complex and resource-intensive, and are susceptible to adversarial attacks.
On one hand, to counter complexity and resource-related limitations, various techniques such as Quantization and Approximate Computing (AxC) have been proposed to reduce the complexity and power consumption of CNNs, respectively.
On the other hand, various techniques have been proposed to craft more precise and stronger adversarial attacks, as well as new methodologies to defend against them.
Nevertheless, the relationship between the efficiency and security of CNNs is not adequately addressed.
Therefore, this article examines the potential for detecting adversarial attacks against CNNs through image transformation, in the context of quantized and approximate neural networks.
The experimental results indicate that image-transformation techniques are not effective in detecting adversarial samples against quantized and approximated CNNs, despite their success in detecting such samples against floating-point CNNs.},
keywords = {},
pubstate = {published},
tppubtype = {inproceedings}
}
Convolutional Neural Networks (CNNs) have achieved superhuman performance in computer vision tasks. However, these networks are becoming both increasingly complex and resource-intensive, and are susceptible to adversarial attacks.
On one hand, to counter complexity and resource-related limitations, various techniques such as Quantization and Approximate Computing (AxC) have been proposed to reduce the complexity and power consumption of CNNs, respectively.
On the other hand, various techniques have been proposed to craft more precise and stronger adversarial attacks, as well as new methodologies to defend against them.
Nevertheless, the relationship between the efficiency and security of CNNs is not adequately addressed.
Therefore, this article examines the potential for detecting adversarial attacks against CNNs through image transformation, in the context of quantized and approximate neural networks.
The experimental results indicate that image-transformation techniques are not effective in detecting adversarial samples against quantized and approximated CNNs, despite their success in detecting such samples against floating-point CNNs.
On one hand, to counter complexity and resource-related limitations, various techniques such as Quantization and Approximate Computing (AxC) have been proposed to reduce the complexity and power consumption of CNNs, respectively.
On the other hand, various techniques have been proposed to craft more precise and stronger adversarial attacks, as well as new methodologies to defend against them.
Nevertheless, the relationship between the efficiency and security of CNNs is not adequately addressed.
Therefore, this article examines the potential for detecting adversarial attacks against CNNs through image transformation, in the context of quantized and approximate neural networks.
The experimental results indicate that image-transformation techniques are not effective in detecting adversarial samples against quantized and approximated CNNs, despite their success in detecting such samples against floating-point CNNs.
Barbareschi, Mario; Barone, Salvatore; Emmanuele, Antonio; Mazzocca, Nicola
Exploiting Functional Approximation on Decision-Tree based Multiple Classifier Systems Proceedings Article
In: Proceedingsof the IFIP/IEEE International Conference on Very Large Scale Integration (In Press), IFIP/IEEE, Tanger, Marocco, 2024.
@inproceedings{barbareschi_exploiting_2024,
title = {Exploiting Functional Approximation on Decision-Tree based Multiple Classifier Systems},
author = {Mario Barbareschi and Salvatore Barone and Antonio Emmanuele and Nicola Mazzocca},
year = {2024},
date = {2024-01-01},
booktitle = {Proceedingsof the IFIP/IEEE International Conference on Very Large Scale Integration (In Press)},
publisher = {IFIP/IEEE},
address = {Tanger, Marocco},
abstract = {Multiple Classifier Systems (MCSs) have been increasingly designed to take advantage of hardware features, such as high parallelism and computational power, to guarantee higher throughput and lower latency.
Although the combination of multiple classifiers leads to high classification accuracy, the required area overhead makes the design of a hardware accelerator unfeasible, hindering the adoption of commercial configurable devices.
For this reason, in this paper, we exploit the Approximate Computing (AxC) design paradigm to automatically generate approximated hardware implementations of MCSs by trading hardware area overhead off for classification accuracy. In particular, we propose an algorithm that identifies the resiliency source of the model and uses it to introduce approximation with minimum accuracy loss. In order to prove the effectiveness of our solution, we performed numerous experiments on models of various sizes trained on different datasets. The results show that with negligible accuracy loss it is possible to significantly reduce the hardware requirements of a classifier.},
keywords = {},
pubstate = {published},
tppubtype = {inproceedings}
}
Multiple Classifier Systems (MCSs) have been increasingly designed to take advantage of hardware features, such as high parallelism and computational power, to guarantee higher throughput and lower latency.
Although the combination of multiple classifiers leads to high classification accuracy, the required area overhead makes the design of a hardware accelerator unfeasible, hindering the adoption of commercial configurable devices.
For this reason, in this paper, we exploit the Approximate Computing (AxC) design paradigm to automatically generate approximated hardware implementations of MCSs by trading hardware area overhead off for classification accuracy. In particular, we propose an algorithm that identifies the resiliency source of the model and uses it to introduce approximation with minimum accuracy loss. In order to prove the effectiveness of our solution, we performed numerous experiments on models of various sizes trained on different datasets. The results show that with negligible accuracy loss it is possible to significantly reduce the hardware requirements of a classifier.
Although the combination of multiple classifiers leads to high classification accuracy, the required area overhead makes the design of a hardware accelerator unfeasible, hindering the adoption of commercial configurable devices.
For this reason, in this paper, we exploit the Approximate Computing (AxC) design paradigm to automatically generate approximated hardware implementations of MCSs by trading hardware area overhead off for classification accuracy. In particular, we propose an algorithm that identifies the resiliency source of the model and uses it to introduce approximation with minimum accuracy loss. In order to prove the effectiveness of our solution, we performed numerous experiments on models of various sizes trained on different datasets. The results show that with negligible accuracy loss it is possible to significantly reduce the hardware requirements of a classifier.
2023
Barone, Salvatore; Casola, Valentina; Torca, Salvatore Della; Lombardi, Daniele
Timing Behavior Characterization of Critical Real-Time Systems through Hybrid Timing Analysis Proceedings Article
In: 2023 7th International Conference on System Reliability and Safety (ICSRS), pp. 306–311, IEEE, Bologna, Italy, 2023, ISBN: 979-8-3503-0605-7.
Abstract | Links | BibTeX | Tags: Dependable Systems, Real-time systems
@inproceedings{baroneTimingBehaviorCharacterization2023,
title = {Timing Behavior Characterization of Critical Real-Time Systems through Hybrid Timing Analysis},
author = {Salvatore Barone and Valentina Casola and Salvatore Della Torca and Daniele Lombardi},
url = {https://ieeexplore.ieee.org/document/10381272/},
doi = {10.1109/ICSRS59833.2023.10381272},
isbn = {979-8-3503-0605-7},
year = {2023},
date = {2023-11-01},
urldate = {2024-07-04},
booktitle = {2023 7th International Conference on System Reliability and Safety (ICSRS)},
pages = {306–311},
publisher = {IEEE},
address = {Bologna, Italy},
abstract = {The spread of computing-systems, especially the real-time embedded ones, is rapidly growing in the last years, since they find usage in numerous fields of application, including, but not limited to, industry process, critical infrastructures, transportation systems, as so forth. Indeed, in these fields, precise time-constraints hold; hence, tasks need to be correct from both the functional and temporal perspectives. As for the latter, timing behavior has to be characterized, that is usually done by exploiting either static or dynamic analysis techniques, which leverage estimations based on either a model or the actual system. In this paper, we foster an automated hybrid approach that allows characterizing the timing behavior of systems while introducing any alteration, i.e., relying on instruction-level tracing rather than code instrumentation for profiling purposes. Our approach is sensitive to the execution-context, – e.g., cache misses – and it allows re-using results from the development processes – e.g., unit tests. We considered a complex real-time application from the railway domain as a case study to evaluate our approach, empirically proving that it can provide a faithful characterization of systems in terms of worst-case execution time.},
keywords = {Dependable Systems, Real-time systems},
pubstate = {published},
tppubtype = {inproceedings}
}
The spread of computing-systems, especially the real-time embedded ones, is rapidly growing in the last years, since they find usage in numerous fields of application, including, but not limited to, industry process, critical infrastructures, transportation systems, as so forth. Indeed, in these fields, precise time-constraints hold; hence, tasks need to be correct from both the functional and temporal perspectives. As for the latter, timing behavior has to be characterized, that is usually done by exploiting either static or dynamic analysis techniques, which leverage estimations based on either a model or the actual system. In this paper, we foster an automated hybrid approach that allows characterizing the timing behavior of systems while introducing any alteration, i.e., relying on instruction-level tracing rather than code instrumentation for profiling purposes. Our approach is sensitive to the execution-context, – e.g., cache misses – and it allows re-using results from the development processes – e.g., unit tests. We considered a complex real-time application from the railway domain as a case study to evaluate our approach, empirically proving that it can provide a faithful characterization of systems in terms of worst-case execution time.
Barone, Salvatore; Casola, Valentina; Torca, Salvatore Della; Lombardi, Daniele
Timing Behavior Characterization of Critical Real-Time Systems through Hybrid Timing Analysis Proceedings Article
In: 2023 7th International Conference on System Reliability and Safety (ICSRS), pp. 306–311, IEEE, Bologna, Italy, 2023, ISBN: 979-8-3503-0605-7.
Abstract | Links | BibTeX | Tags: Dependable Systems, Real-time systems
@inproceedings{barone_timing_2023,
title = {Timing Behavior Characterization of Critical Real-Time Systems through Hybrid Timing Analysis},
author = {Salvatore Barone and Valentina Casola and Salvatore Della Torca and Daniele Lombardi},
url = {https://ieeexplore.ieee.org/document/10381272/},
doi = {10.1109/ICSRS59833.2023.10381272},
isbn = {979-8-3503-0605-7},
year = {2023},
date = {2023-11-01},
urldate = {2024-07-04},
booktitle = {2023 7th International Conference on System Reliability and Safety (ICSRS)},
pages = {306–311},
publisher = {IEEE},
address = {Bologna, Italy},
abstract = {The spread of computing-systems, especially the real-time embedded ones, is rapidly growing in the last years, since they find usage in numerous fields of application, including, but not limited to, industry process, critical infrastructures, transportation systems, as so forth. Indeed, in these fields, precise time-constraints hold; hence, tasks need to be correct from both the functional and temporal perspectives. As for the latter, timing behavior has to be characterized, that is usually done by exploiting either static or dynamic analysis techniques, which leverage estimations based on either a model or the actual system. In this paper, we foster an automated hybrid approach that allows characterizing the timing behavior of systems while introducing any alteration, i.e., relying on instruction-level tracing rather than code instrumentation for profiling purposes. Our approach is sensitive to the execution-context, – e.g., cache misses – and it allows re-using results from the development processes – e.g., unit tests. We considered a complex real-time application from the railway domain as a case study to evaluate our approach, empirically proving that it can provide a faithful characterization of systems in terms of worst-case execution time.},
keywords = {Dependable Systems, Real-time systems},
pubstate = {published},
tppubtype = {inproceedings}
}
The spread of computing-systems, especially the real-time embedded ones, is rapidly growing in the last years, since they find usage in numerous fields of application, including, but not limited to, industry process, critical infrastructures, transportation systems, as so forth. Indeed, in these fields, precise time-constraints hold; hence, tasks need to be correct from both the functional and temporal perspectives. As for the latter, timing behavior has to be characterized, that is usually done by exploiting either static or dynamic analysis techniques, which leverage estimations based on either a model or the actual system. In this paper, we foster an automated hybrid approach that allows characterizing the timing behavior of systems while introducing any alteration, i.e., relying on instruction-level tracing rather than code instrumentation for profiling purposes. Our approach is sensitive to the execution-context, – e.g., cache misses – and it allows re-using results from the development processes – e.g., unit tests. We considered a complex real-time application from the railway domain as a case study to evaluate our approach, empirically proving that it can provide a faithful characterization of systems in terms of worst-case execution time.
Barbareschi, Mario; Barone, Salvatore; Casola, Valentina; Torca, Salvatore Della; Lombardi, Daniele
Automatic Test Generation to Improve Scrum for Safety Agile Methodology Proceedings Article
In: Proceedings of the 18th International Conference on Availability, Reliability and Security, pp. 1–6, ACM, Benevento Italy, 2023, ISBN: 979-8-4007-0772-8, (tex.copyright: All rights reserved).
Links | BibTeX | Tags: Agile Methodologies, Computer Science - Software, Dependable Systems, Digital, Industry and Space
@inproceedings{barbareschi_automatic_2023,
title = {Automatic Test Generation to Improve Scrum for Safety Agile Methodology},
author = {Mario Barbareschi and Salvatore Barone and Valentina Casola and Salvatore Della Torca and Daniele Lombardi},
url = {https://dl.acm.org/doi/10.1145/3600160.3605061},
doi = {10.1145/3600160.3605061},
isbn = {979-8-4007-0772-8},
year = {2023},
date = {2023-08-01},
urldate = {2024-07-04},
booktitle = {Proceedings of the 18th International Conference on Availability, Reliability and Security},
pages = {1–6},
publisher = {ACM},
address = {Benevento Italy},
note = {tex.copyright: All rights reserved},
keywords = {Agile Methodologies, Computer Science - Software, Dependable Systems, Digital, Industry and Space},
pubstate = {published},
tppubtype = {inproceedings}
}
Piri, Ali; Pappalardo, Salvatore; Barone, Salvatore; Barbareschi, Mario; Deveautour, Bastien; Traiola, Marcello; O’Connor, Ian; Bosio, Alberto
Input-aware accuracy characterization for approximate circuits Proceedings Article
In: 2023 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W), pp. 179–182, IEEE, Porto, Portugal, 2023, ISBN: 979-8-3503-2543-0.
Abstract | Links | BibTeX | Tags: Integrated circuit design, Low power approximate circuits
@inproceedings{piri_input-aware_2023,
title = {Input-aware accuracy characterization for approximate circuits},
author = {Ali Piri and Salvatore Pappalardo and Salvatore Barone and Mario Barbareschi and Bastien Deveautour and Marcello Traiola and Ian O’Connor and Alberto Bosio},
url = {https://ieeexplore.ieee.org/document/10207125/},
doi = {10.1109/DSN-W58399.2023.00050},
isbn = {979-8-3503-2543-0},
year = {2023},
date = {2023-01-01},
urldate = {2024-02-07},
booktitle = {2023 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W)},
pages = {179–182},
publisher = {IEEE},
address = {Porto, Portugal},
abstract = {It has been a while since Approximate Computing (AxC) is applied systematically at various abstraction levels to increase the efficiency of several applications such as image processing and machine learning. Despite its benefit, AxC is still agnostic concerning the specific workload (i.e., input data to be processed) of a given application. For instance, in signal processing applications (such as a filter), some inputs are constants (filter coefficients). Meaning that a further level of approximation can be introduced by considering the specific input distribution. This approach has been referred to as “input-aware approximation”. In this paper, we explore how the input-aware approximate design approach can become part of a systematic, generic, and automatic design flow by knowing the data distribution. In particular, we show how input distribution can affect the error characteristics of an approximate arithmetic circuit and also the advantage of considering the data distribution by designing an input-aware approximate multiplier specifically intended for a high-pass FIR filter, where the coefficients are constant. Experimental results show that we can significantly reduce power consumption while keeping an error rate lower than state-of-the-art approximate multipliers.},
keywords = {Integrated circuit design, Low power approximate circuits},
pubstate = {published},
tppubtype = {inproceedings}
}
It has been a while since Approximate Computing (AxC) is applied systematically at various abstraction levels to increase the efficiency of several applications such as image processing and machine learning. Despite its benefit, AxC is still agnostic concerning the specific workload (i.e., input data to be processed) of a given application. For instance, in signal processing applications (such as a filter), some inputs are constants (filter coefficients). Meaning that a further level of approximation can be introduced by considering the specific input distribution. This approach has been referred to as “input-aware approximation”. In this paper, we explore how the input-aware approximate design approach can become part of a systematic, generic, and automatic design flow by knowing the data distribution. In particular, we show how input distribution can affect the error characteristics of an approximate arithmetic circuit and also the advantage of considering the data distribution by designing an input-aware approximate multiplier specifically intended for a high-pass FIR filter, where the coefficients are constant. Experimental results show that we can significantly reduce power consumption while keeping an error rate lower than state-of-the-art approximate multipliers.
Ahmadilivani, Mohammad Hasan; Barbareschi, Mario; Barone, Salvatore; Bosio, Alberto; Daneshtalab, Masoud; Torca, Salvatore Della; Gavarini, Gabriele; Jenihhin, Maksim; Raik, Jaan; Ruospo, Annachiara
Special Session: Approximation and Fault Resiliency of DNN Accelerators Proceedings Article
In: 2023 IEEE 41st VLSI Test Symposium (VTS), pp. 1–10, IEEE, 2023.
BibTeX | Tags: Artificial Intelligence, Dependable Systems
@inproceedings{ahmadilivaniSpecialSessionApproximation2023,
title = {Special Session: Approximation and Fault Resiliency of DNN Accelerators},
author = {Mohammad Hasan Ahmadilivani and Mario Barbareschi and Salvatore Barone and Alberto Bosio and Masoud Daneshtalab and Salvatore Della Torca and Gabriele Gavarini and Maksim Jenihhin and Jaan Raik and Annachiara Ruospo},
year = {2023},
date = {2023-01-01},
booktitle = {2023 IEEE 41st VLSI Test Symposium (VTS)},
pages = {1–10},
publisher = {IEEE},
keywords = {Artificial Intelligence, Dependable Systems},
pubstate = {published},
tppubtype = {inproceedings}
}
Ahmadilivani, Mohammad Hasan; Barbareschi, Mario; Barone, Salvatore; Bosio, Alberto; Daneshtalab, Masoud; Torca, Salvatore Della; Gavarini, Gabriele; Jenihhin, Maksim; Raik, Jaan; Ruospo, Annachiara
Special Session: Approximation and Fault Resiliency of DNN Accelerators Proceedings Article
In: 2023 IEEE 41st VLSI Test Symposium (VTS), pp. 1–10, IEEE, 2023.
BibTeX | Tags: Artificial Intelligence, Dependable Systems
@inproceedings{ahmadilivani_special_2023,
title = {Special Session: Approximation and Fault Resiliency of DNN Accelerators},
author = {Mohammad Hasan Ahmadilivani and Mario Barbareschi and Salvatore Barone and Alberto Bosio and Masoud Daneshtalab and Salvatore Della Torca and Gabriele Gavarini and Maksim Jenihhin and Jaan Raik and Annachiara Ruospo},
year = {2023},
date = {2023-01-01},
booktitle = {2023 IEEE 41st VLSI Test Symposium (VTS)},
pages = {1–10},
publisher = {IEEE},
keywords = {Artificial Intelligence, Dependable Systems},
pubstate = {published},
tppubtype = {inproceedings}
}
2022
Barbareschi, Mario; Barone, Salvatore; Carbone, Riccardo; Casola, Valentina
Scrum for safety: an agile methodology for safety-critical software systems Journal Article
In: Software Quality Journal, vol. 30, no. 4, pp. 1067–1088, 2022, ISSN: 1573-1367.
Abstract | Links | BibTeX | Tags: Agile Methodologies, Software Development Cycle, Software Engineering
@article{barbareschiScrumSafetyAgile2022,
title = {Scrum for safety: an agile methodology for safety-critical software systems},
author = {Mario Barbareschi and Salvatore Barone and Riccardo Carbone and Valentina Casola},
url = {https://doi.org/10.1007/s11219-022-09593-2},
doi = {10.1007/s11219-022-09593-2},
issn = {1573-1367},
year = {2022},
date = {2022-12-01},
urldate = {2024-06-03},
journal = {Software Quality Journal},
volume = {30},
number = {4},
pages = {1067–1088},
abstract = {In the last years, agile methodologies are gaining substantial momentum, becoming increasingly popular in a broad plethora of industrial contexts. Unfortunately, many obstacles have been met while pursuing adoption in secure and safe systems, where different standards and operational constraints apply. In this paper, we propose a novel agile methodology for the development and innovation of safety-critical systems. In particular, we developed an extension of the well-known Scrum methodology and discussed the complete workflow. We finally validated the applicability of the proposed methodology over a real case study from the railway domain.},
keywords = {Agile Methodologies, Software Development Cycle, Software Engineering},
pubstate = {published},
tppubtype = {article}
}
In the last years, agile methodologies are gaining substantial momentum, becoming increasingly popular in a broad plethora of industrial contexts. Unfortunately, many obstacles have been met while pursuing adoption in secure and safe systems, where different standards and operational constraints apply. In this paper, we propose a novel agile methodology for the development and innovation of safety-critical systems. In particular, we developed an extension of the well-known Scrum methodology and discussed the complete workflow. We finally validated the applicability of the proposed methodology over a real case study from the railway domain.
Barbareschi, Mario; Barone, Salvatore; Carbone, Riccardo; Casola, Valentina
Scrum for safety: an agile methodology for safety-critical software systems Journal Article
In: Software Quality Journal, vol. 30, no. 4, pp. 1067–1088, 2022, ISSN: 1573-1367.
Abstract | Links | BibTeX | Tags: Agile Methodologies, Software Development Cycle, Software Engineering
@article{barbareschi_scrum_2022,
title = {Scrum for safety: an agile methodology for safety-critical software systems},
author = {Mario Barbareschi and Salvatore Barone and Riccardo Carbone and Valentina Casola},
url = {https://doi.org/10.1007/s11219-022-09593-2},
doi = {10.1007/s11219-022-09593-2},
issn = {1573-1367},
year = {2022},
date = {2022-12-01},
urldate = {2024-06-03},
journal = {Software Quality Journal},
volume = {30},
number = {4},
pages = {1067–1088},
abstract = {In the last years, agile methodologies are gaining substantial momentum, becoming increasingly popular in a broad plethora of industrial contexts. Unfortunately, many obstacles have been met while pursuing adoption in secure and safe systems, where different standards and operational constraints apply. In this paper, we propose a novel agile methodology for the development and innovation of safety-critical systems. In particular, we developed an extension of the well-known Scrum methodology and discussed the complete workflow. We finally validated the applicability of the proposed methodology over a real case study from the railway domain.},
keywords = {Agile Methodologies, Software Development Cycle, Software Engineering},
pubstate = {published},
tppubtype = {article}
}
In the last years, agile methodologies are gaining substantial momentum, becoming increasingly popular in a broad plethora of industrial contexts. Unfortunately, many obstacles have been met while pursuing adoption in secure and safe systems, where different standards and operational constraints apply. In this paper, we propose a novel agile methodology for the development and innovation of safety-critical systems. In particular, we developed an extension of the well-known Scrum methodology and discussed the complete workflow. We finally validated the applicability of the proposed methodology over a real case study from the railway domain.