Publications
OUR RESEARCH
Scientific Publications
Here you can find the comprehensive list of publications from the members of the Research Center on Computer Vision and eXtended Reality (xRAI).
Use the tag cloud to filter papers based on specific research topics, or use the menus to filter by year, type of publication, or authors.
For each paper, you have the option to view additional details such as the Abstract, Links, and BibTex record.
Research is formalized curiosity. It is poking and prying with a purpose
Zora Neale Hurston
2022
Barbareschi, Mario; Barone, Salvatore; Casola, Valentina; Montone, Pasquale; Moriconi, Alberto
A Memory Protection Strategy for Resource Constrained Devices in Safety Critical Applications Proceedings Article
In: 2022 6th International Conference on System Reliability and Safety (ICSRS), pp. 533–538, IEEE, Venice, Italy, 2022, ISBN: 978-1-6654-7092-6.
Abstract | Links | BibTeX | Tags: Computer Science - Software, Dependable Systems, Digital, Industry and Space, Real-time systems
@inproceedings{barbareschi_memory_2022,
title = {A Memory Protection Strategy for Resource Constrained Devices in Safety Critical Applications},
author = {Mario Barbareschi and Salvatore Barone and Valentina Casola and Pasquale Montone and Alberto Moriconi},
url = {https://ieeexplore.ieee.org/document/10067350/},
doi = {10.1109/ICSRS56243.2022.10067350},
isbn = {978-1-6654-7092-6},
year = {2022},
date = {2022-11-01},
urldate = {2024-07-04},
booktitle = {2022 6th International Conference on System Reliability and Safety (ICSRS)},
pages = {533–538},
publisher = {IEEE},
address = {Venice, Italy},
abstract = {In modern safety-related applications, software has achieved an increasingly critical role. Their safety-critical nature, however, requires special attention: industry-specific functionalsafety standards guide designers, developers, integrators, and testers during all phases of the software life-cycle and the final artifacts undergo a rigorous certification process.},
keywords = {Computer Science - Software, Dependable Systems, Digital, Industry and Space, Real-time systems},
pubstate = {published},
tppubtype = {inproceedings}
}
In modern safety-related applications, software has achieved an increasingly critical role. Their safety-critical nature, however, requires special attention: industry-specific functionalsafety standards guide designers, developers, integrators, and testers during all phases of the software life-cycle and the final artifacts undergo a rigorous certification process.
Barbareschi, Mario; Barone, Salvatore; Bosio, Alberto; Han, Jie; Traiola, Marcello
A Genetic-algorithm-based Approach to the Design of DCT Hardware Accelerators Journal Article
In: ACM Journal on Emerging Technologies in Computing Systems, vol. 18, no. 3, pp. 1–25, 2022, ISSN: 1550-4832, 1550-4840, (tex.copyright: All rights reserved).
Abstract | Links | BibTeX | Tags: Computer science, Digital, Hardware and Architecture, Image Processing, Industry and Space, Low area approximate circuit, Low power approximate circuits
@article{barbareschi_genetic-algorithm-based_2022,
title = {A Genetic-algorithm-based Approach to the Design of DCT Hardware Accelerators},
author = {Mario Barbareschi and Salvatore Barone and Alberto Bosio and Jie Han and Marcello Traiola},
url = {https://dl.acm.org/doi/10.1145/3501772},
doi = {10.1145/3501772},
issn = {1550-4832, 1550-4840},
year = {2022},
date = {2022-07-01},
urldate = {2022-04-25},
journal = {ACM Journal on Emerging Technologies in Computing Systems},
volume = {18},
number = {3},
pages = {1–25},
abstract = {As modern applications demand an unprecedented level of computational resources, traditional computing system design paradigms are no longer adequate to guarantee significant performance enhancement at an affordable cost. Approximate Computing (AxC) has been introduced as a potential candidate to achieve better computational performances by relaxing non-critical functional system specifications. In this article, we propose a systematic and high-abstraction-level approach allowing the automatic generation of near Pareto-optimal approximate configurations for a Discrete Cosine Transform (DCT) hardware accelerator. We obtain the approximate variants by using approximate operations, having configurable approximation degree, rather than full-precise ones. We use a genetic searching algorithm to find the appropriate tuning of the approximation degree, leading to optimal tradeoffs between accuracy and gains. Finally, to evaluate the actual HW gains, we synthesize non-dominated approximate DCT variants for two different target technologies, namely, Field Programmable Gate Arrays (FPGAs) and Application Specific Integrated Circuits (ASICs). Experimental results show that the proposed approach allows performing a meaningful exploration of the design space to find the best tradeoffs in a reasonable time. Indeed, compared to the state-of-the-art work on approximate DCT, the proposed approach allows an 18% average energy improvement while providing at the same time image quality improvement.},
note = {tex.copyright: All rights reserved},
keywords = {Computer science, Digital, Hardware and Architecture, Image Processing, Industry and Space, Low area approximate circuit, Low power approximate circuits},
pubstate = {published},
tppubtype = {article}
}
As modern applications demand an unprecedented level of computational resources, traditional computing system design paradigms are no longer adequate to guarantee significant performance enhancement at an affordable cost. Approximate Computing (AxC) has been introduced as a potential candidate to achieve better computational performances by relaxing non-critical functional system specifications. In this article, we propose a systematic and high-abstraction-level approach allowing the automatic generation of near Pareto-optimal approximate configurations for a Discrete Cosine Transform (DCT) hardware accelerator. We obtain the approximate variants by using approximate operations, having configurable approximation degree, rather than full-precise ones. We use a genetic searching algorithm to find the appropriate tuning of the approximation degree, leading to optimal tradeoffs between accuracy and gains. Finally, to evaluate the actual HW gains, we synthesize non-dominated approximate DCT variants for two different target technologies, namely, Field Programmable Gate Arrays (FPGAs) and Application Specific Integrated Circuits (ASICs). Experimental results show that the proposed approach allows performing a meaningful exploration of the design space to find the best tradeoffs in a reasonable time. Indeed, compared to the state-of-the-art work on approximate DCT, the proposed approach allows an 18% average energy improvement while providing at the same time image quality improvement.
Barbareschi, Mario; Barone, Salvatore; Mazzocca, Nicola; Moriconi, Alberto
A Catalog-based AIG-Rewriting Approach to the Design of Approximate Components Journal Article
In: IEEE Transactions on Emerging Topics in Computing, 2022, (tex.copyright: All rights reserved).
Abstract | Links | BibTeX | Tags: Computer Aided Design Methodologies, Computer science, Digital, Hardware and Architecture, Industry and Space, Low area approximate circuit, Low power approximate circuits
@article{barbareschi_catalog-based_2022,
title = {A Catalog-based AIG-Rewriting Approach to the Design of Approximate Components},
author = {Mario Barbareschi and Salvatore Barone and Nicola Mazzocca and Alberto Moriconi},
doi = {10.1109/TETC.2022.3170502},
year = {2022},
date = {2022-01-01},
journal = {IEEE Transactions on Emerging Topics in Computing},
abstract = {As computational demand and energy efficiency of computer systems are becoming increasingly relevant requirements, traditional design paradigms are bound to become no longer appropriate, as they cannot guarantee significant improvements.
The approximate-computing design paradigm has been introduced as a potential candidate to achieve better performances, by relaxing non-critical functional specifications. Anyway, several challenges need to be addressed in order to exploit its potential.
In this paper, we propose a systematic and application-independent approximate design approach suitable to combinational logic circuits.
Our approach is based on non-trivial local rewriting of and-inverter graphs (AIG), reducing the number of AIG-nodes and possibly resulting in lower hardware resources requirements.
We adopt multi-objective optimization to carefully introduce approximation while aiming at optimal trade-offs between error and hardware-requirements.
We evaluate our approach using different benchmarks, and, in order to measure actual gains, we perform actual synthesis of Pareto-optimal approximate configurations.
Experimental results show that the proposed approach allows achieving significant savings, since resulting approximate circuits exhibit lower requirements and restrained error w.r.t. their exact couterparts.},
note = {tex.copyright: All rights reserved},
keywords = {Computer Aided Design Methodologies, Computer science, Digital, Hardware and Architecture, Industry and Space, Low area approximate circuit, Low power approximate circuits},
pubstate = {published},
tppubtype = {article}
}
As computational demand and energy efficiency of computer systems are becoming increasingly relevant requirements, traditional design paradigms are bound to become no longer appropriate, as they cannot guarantee significant improvements.
The approximate-computing design paradigm has been introduced as a potential candidate to achieve better performances, by relaxing non-critical functional specifications. Anyway, several challenges need to be addressed in order to exploit its potential.
In this paper, we propose a systematic and application-independent approximate design approach suitable to combinational logic circuits.
Our approach is based on non-trivial local rewriting of and-inverter graphs (AIG), reducing the number of AIG-nodes and possibly resulting in lower hardware resources requirements.
We adopt multi-objective optimization to carefully introduce approximation while aiming at optimal trade-offs between error and hardware-requirements.
We evaluate our approach using different benchmarks, and, in order to measure actual gains, we perform actual synthesis of Pareto-optimal approximate configurations.
Experimental results show that the proposed approach allows achieving significant savings, since resulting approximate circuits exhibit lower requirements and restrained error w.r.t. their exact couterparts.
The approximate-computing design paradigm has been introduced as a potential candidate to achieve better performances, by relaxing non-critical functional specifications. Anyway, several challenges need to be addressed in order to exploit its potential.
In this paper, we propose a systematic and application-independent approximate design approach suitable to combinational logic circuits.
Our approach is based on non-trivial local rewriting of and-inverter graphs (AIG), reducing the number of AIG-nodes and possibly resulting in lower hardware resources requirements.
We adopt multi-objective optimization to carefully introduce approximation while aiming at optimal trade-offs between error and hardware-requirements.
We evaluate our approach using different benchmarks, and, in order to measure actual gains, we perform actual synthesis of Pareto-optimal approximate configurations.
Experimental results show that the proposed approach allows achieving significant savings, since resulting approximate circuits exhibit lower requirements and restrained error w.r.t. their exact couterparts.
Barbareschi, Mario; Barone, Salvatore; Mazzocca, Nicola; Moriconi, Alberto
Design Space Exploration Tools Book Section
In: Bosio, Alberto; Ménard, Daniel; Sentieys, Olivier (Ed.): Approximate Computing Techniques: From Component- to Application-Level, pp. 215–259, Springer International Publishing, Cham, 2022, ISBN: 978-3-030-94705-7, (tex.copyright: All rights reserved).
Abstract | Links | BibTeX | Tags: Computer Science Applications, Design-space Exploration, Digital, Industry and Space, Multi-objective optimization
@incollection{barbareschi_design_2022,
title = {Design Space Exploration Tools},
author = {Mario Barbareschi and Salvatore Barone and Nicola Mazzocca and Alberto Moriconi},
editor = {Alberto Bosio and Daniel Ménard and Olivier Sentieys},
url = {https://doi.org/10.1007/978-3-030-94705-7_8},
doi = {10.1007/978-3-030-94705-7_8},
isbn = {978-3-030-94705-7},
year = {2022},
date = {2022-01-01},
urldate = {2023-01-16},
booktitle = {Approximate Computing Techniques: From Component- to Application-Level},
pages = {215–259},
publisher = {Springer International Publishing},
address = {Cham},
abstract = {The Approximate Computing design paradigm has repeatedly shown to be well suited to the needs of modern applications, especially those that interact with the physical world and process large amounts of data. By leveraging the presence of error-tolerant data and algorithms and the perceptual limitations of end-users, it allows to selectively relax the correctness requirements, achieving great performance enhancement and admitting a negligible output quality loss. Unfortunately, applying Approximate Computing to its full potential requires addressing several challenges: there is neither a generic methodology for identifying approximable code or circuit parts nor an approach for selecting the most suitable approximate techniques to apply. However, several tools have been proposed that seek to automate or at least guide part of the approximation process. In this chapter, we first discuss the state of the art for automatic tools for Approximate Computing, targeting digital circuits and software applications. We then introduce 𝕀DE𝔸$$textbackslashmathbb Itextbackslashtext DEtextbackslashmathbb A$$, an extendible tool suite that allows to describe Approximate Computing techniques, apply them to C/C++ code, and explore the design space of the obtained approximate variants to find an estimate of the Pareto front.},
note = {tex.copyright: All rights reserved},
keywords = {Computer Science Applications, Design-space Exploration, Digital, Industry and Space, Multi-objective optimization},
pubstate = {published},
tppubtype = {incollection}
}
The Approximate Computing design paradigm has repeatedly shown to be well suited to the needs of modern applications, especially those that interact with the physical world and process large amounts of data. By leveraging the presence of error-tolerant data and algorithms and the perceptual limitations of end-users, it allows to selectively relax the correctness requirements, achieving great performance enhancement and admitting a negligible output quality loss. Unfortunately, applying Approximate Computing to its full potential requires addressing several challenges: there is neither a generic methodology for identifying approximable code or circuit parts nor an approach for selecting the most suitable approximate techniques to apply. However, several tools have been proposed that seek to automate or at least guide part of the approximation process. In this chapter, we first discuss the state of the art for automatic tools for Approximate Computing, targeting digital circuits and software applications. We then introduce 𝕀DE𝔸$$textbackslashmathbb Itextbackslashtext DEtextbackslashmathbb A$$, an extendible tool suite that allows to describe Approximate Computing techniques, apply them to C/C++ code, and explore the design space of the obtained approximate variants to find an estimate of the Pareto front.
2021
Carbone, Riccardo; Barone, Salvatore; Barbareschi, Mario; Casola, Valentina
Scrum for Safety: Agile Development in Safety-Critical Software Systems Proceedings Article
In: Paiva, Ana C. R.; Cavalli, Ana Rosa; Martins, Paula Ventura; Pérez-Castillo, Ricardo (Ed.): Quality of Information and Communications Technology, pp. 127–140, Springer International Publishing, Algarve, Portugal, 2021, ISBN: 978-3-030-85347-1.
Abstract | Links | BibTeX | Tags: Agile Methodologies, Software Development Cycle
@inproceedings{carboneScrumSafetyAgile2021,
title = {Scrum for Safety: Agile Development in Safety-Critical Software Systems},
author = {Riccardo Carbone and Salvatore Barone and Mario Barbareschi and Valentina Casola},
editor = {Ana C. R. Paiva and Ana Rosa Cavalli and Paula Ventura Martins and Ricardo Pérez-Castillo},
doi = {10.1007/978-3-030-85347-1_10},
isbn = {978-3-030-85347-1},
year = {2021},
date = {2021-09-01},
booktitle = {Quality of Information and Communications Technology},
pages = {127–140},
publisher = {Springer International Publishing},
address = {Algarve, Portugal},
abstract = {The adoption of agile methodologies in all domains of software development is a desired goal. Unfortunately, many obstacles have been meet in the past for a full adoption in secure and safe systems, where different standards and operational constraints apply. In this paper we propose a novel agile methodology to be applied in the development of safety critical systems. In particular, we developed an extension of the well-known Scrum methodology and discussed the complete workflow. We finally validated the applicability of the methodology over a real case study from the railway domain.},
keywords = {Agile Methodologies, Software Development Cycle},
pubstate = {published},
tppubtype = {inproceedings}
}
The adoption of agile methodologies in all domains of software development is a desired goal. Unfortunately, many obstacles have been meet in the past for a full adoption in secure and safe systems, where different standards and operational constraints apply. In this paper we propose a novel agile methodology to be applied in the development of safety critical systems. In particular, we developed an extension of the well-known Scrum methodology and discussed the complete workflow. We finally validated the applicability of the methodology over a real case study from the railway domain.
Carbone, Riccardo; Barone, Salvatore; Barbareschi, Mario; Casola, Valentina
Scrum for Safety: Agile Development in Safety-Critical Software Systems Proceedings Article
In: Paiva, Ana C. R.; Cavalli, Ana Rosa; Martins, Paula Ventura; Pérez-Castillo, Ricardo (Ed.): Quality of Information and Communications Technology, pp. 127–140, Springer International Publishing, Algarve, Portugal, 2021, ISBN: 978-3-030-85347-1.
Abstract | Links | BibTeX | Tags: Agile Methodologies, Software Development Cycle
@inproceedings{carbone_scrum_2021,
title = {Scrum for Safety: Agile Development in Safety-Critical Software Systems},
author = {Riccardo Carbone and Salvatore Barone and Mario Barbareschi and Valentina Casola},
editor = {Ana C. R. Paiva and Ana Rosa Cavalli and Paula Ventura Martins and Ricardo Pérez-Castillo},
doi = {10.1007/978-3-030-85347-1_10},
isbn = {978-3-030-85347-1},
year = {2021},
date = {2021-09-01},
booktitle = {Quality of Information and Communications Technology},
pages = {127–140},
publisher = {Springer International Publishing},
address = {Algarve, Portugal},
abstract = {The adoption of agile methodologies in all domains of software development is a desired goal. Unfortunately, many obstacles have been meet in the past for a full adoption in secure and safe systems, where different standards and operational constraints apply. In this paper we propose a novel agile methodology to be applied in the development of safety critical systems. In particular, we developed an extension of the well-known Scrum methodology and discussed the complete workflow. We finally validated the applicability of the methodology over a real case study from the railway domain.},
keywords = {Agile Methodologies, Software Development Cycle},
pubstate = {published},
tppubtype = {inproceedings}
}
The adoption of agile methodologies in all domains of software development is a desired goal. Unfortunately, many obstacles have been meet in the past for a full adoption in secure and safe systems, where different standards and operational constraints apply. In this paper we propose a novel agile methodology to be applied in the development of safety critical systems. In particular, we developed an extension of the well-known Scrum methodology and discussed the complete workflow. We finally validated the applicability of the methodology over a real case study from the railway domain.
Barbareschi, Mario; Barone, Salvatore; Mazzocca, Nicola
Advancing synthesis of decision tree-based multiple classifier systems: an approximate computing case study Journal Article
In: Knowledge and Information Systems, pp. 1–20, 2021, ISSN: 0219-3116, (tex.copyright: 2021 The Author(s)).
Abstract | Links | BibTeX | Tags: Artificial Intelligence, Computer science, Digital, Hardware and Architecture, Industry and Space, Tree Ensemble
@article{barbareschi_advancing_2021,
title = {Advancing synthesis of decision tree-based multiple classifier systems: an approximate computing case study},
author = {Mario Barbareschi and Salvatore Barone and Nicola Mazzocca},
url = {https://link.springer.com/article/10.1007/s10115-021-01565-5},
doi = {10.1007/s10115-021-01565-5},
issn = {0219-3116},
year = {2021},
date = {2021-04-01},
urldate = {2021-04-12},
journal = {Knowledge and Information Systems},
pages = {1–20},
abstract = {So far, multiple classifier systems have been increasingly designed to take advantage of hardware features, such as high parallelism and computational power. Indeed, compared to software implementations, hardware accelerators guarantee higher throughput and lower latency. Although the combination of multiple classifiers leads to high classification accuracy, the required area overhead makes the design of a hardware accelerator unfeasible, hindering the adoption of commercial configurable devices. For this reason, in this paper, we exploit approximate computing design paradigm to trade hardware area overhead off for classification accuracy. In particular, starting from trained DT models and employing precision-scaling technique, we explore approximate decision tree variants by means of multiple objective optimization problem, demonstrating a significant performance improvement targeting field-programmable gate array devices.},
note = {tex.copyright: 2021 The Author(s)},
keywords = {Artificial Intelligence, Computer science, Digital, Hardware and Architecture, Industry and Space, Tree Ensemble},
pubstate = {published},
tppubtype = {article}
}
So far, multiple classifier systems have been increasingly designed to take advantage of hardware features, such as high parallelism and computational power. Indeed, compared to software implementations, hardware accelerators guarantee higher throughput and lower latency. Although the combination of multiple classifiers leads to high classification accuracy, the required area overhead makes the design of a hardware accelerator unfeasible, hindering the adoption of commercial configurable devices. For this reason, in this paper, we exploit approximate computing design paradigm to trade hardware area overhead off for classification accuracy. In particular, starting from trained DT models and employing precision-scaling technique, we explore approximate decision tree variants by means of multiple objective optimization problem, demonstrating a significant performance improvement targeting field-programmable gate array devices.
Barone, Salvatore; Traiola, Marcello; Barbareschi, Mario; Bosio, Alberto
Multi-Objective Application-Driven Approximate Design Method Journal Article
In: IEEE Access, vol. 9, pp. 86975–86993, 2021, ISSN: 2169-3536.
Abstract | Links | BibTeX | Tags: Computer Aided Design Methodologies, Design-space Exploration
@article{baroneMultiObjectiveApplicationDrivenApproximate2021,
title = {Multi-Objective Application-Driven Approximate Design Method},
author = {Salvatore Barone and Marcello Traiola and Mario Barbareschi and Alberto Bosio},
doi = {10.1109/ACCESS.2021.3087858},
issn = {2169-3536},
year = {2021},
date = {2021-01-01},
journal = {IEEE Access},
volume = {9},
pages = {86975–86993},
abstract = {Approximate Computing (AxC) paradigm aims at designing computing systems that can satisfy the rising performance demands and improve the energy efficiency. AxC exploits the gap between the level of accuracy required by the users, and the actual precision provided by the computing system, for achieving diverse optimizations. Various AxC techniques have been proposed so far in the literature at different abstraction levels from hardware to software. These techniques have been successfully utilized and combined to realize approximate implementations of applications in various domains (e.g. data analytic, scientific computing, multimedia and signal processing, and machine learning). Unfortunately, state-of-the-art approximation methodologies focus on a single abstraction level, such as combining elementary components (e.g., arithmetic operations) which are firstly approximated using component-level metrics and then combined to provide a good trade-off between efficiency and accuracy at the application level. This hinders the possibility for designers to explore different approximation opportunities, optimized for different applications and implementation targets. Therefore, we designed and implemented E- $textbackslashmathbb IDEA$ , an automatic framework that provides an application-driven approximation approach to find the best approximate versions of a given application targeting different implementations (i.e., hardware and software). E- $textbackslashmathbb IDEA$ compounds 1) a source-to-source manipulation tool and 2) an evolutionary search engine to automatically realize approximate application variants and perform a Design-Space Exploration (DSE). The latter results in a set of non-dominate approximate solutions in terms of trade-off between accuracy and efficiency. Experimental results validate the effectiveness and the flexibility of the approach in generating optimized approximate implementations of different applications, by using different approximation techniques and different accuracy/error metrics and for different implementation targets.},
keywords = {Computer Aided Design Methodologies, Design-space Exploration},
pubstate = {published},
tppubtype = {article}
}
Approximate Computing (AxC) paradigm aims at designing computing systems that can satisfy the rising performance demands and improve the energy efficiency. AxC exploits the gap between the level of accuracy required by the users, and the actual precision provided by the computing system, for achieving diverse optimizations. Various AxC techniques have been proposed so far in the literature at different abstraction levels from hardware to software. These techniques have been successfully utilized and combined to realize approximate implementations of applications in various domains (e.g. data analytic, scientific computing, multimedia and signal processing, and machine learning). Unfortunately, state-of-the-art approximation methodologies focus on a single abstraction level, such as combining elementary components (e.g., arithmetic operations) which are firstly approximated using component-level metrics and then combined to provide a good trade-off between efficiency and accuracy at the application level. This hinders the possibility for designers to explore different approximation opportunities, optimized for different applications and implementation targets. Therefore, we designed and implemented E- $textbackslashmathbb IDEA$ , an automatic framework that provides an application-driven approximation approach to find the best approximate versions of a given application targeting different implementations (i.e., hardware and software). E- $textbackslashmathbb IDEA$ compounds 1) a source-to-source manipulation tool and 2) an evolutionary search engine to automatically realize approximate application variants and perform a Design-Space Exploration (DSE). The latter results in a set of non-dominate approximate solutions in terms of trade-off between accuracy and efficiency. Experimental results validate the effectiveness and the flexibility of the approach in generating optimized approximate implementations of different applications, by using different approximation techniques and different accuracy/error metrics and for different implementation targets.
Barbareschi, Mario; Barone, Salvatore; Fezza, Alfonso; Montagna, Erasmo La
Enforcing Mutual Authentication and Confidentiality in Wireless Sensor Networks Using Physically Unclonable Functions: A Case Study Proceedings Article
In: Paiva, Ana C. R.; Cavalli, Ana Rosa; Martins, Paula Ventura; Pérez-Castillo, Ricardo (Ed.): Quality of Information and Communications Technology, pp. 297–310, Springer International Publishing, Cham, 2021, ISBN: 978-3-030-85346-4 978-3-030-85347-1, (Series Title: Communications in Computer and Information Science).
Abstract | Links | BibTeX | Tags: Dependable Systems, Distributed Systems
@inproceedings{barbareschiEnforcingMutualAuthentication2021,
title = {Enforcing Mutual Authentication and Confidentiality in Wireless Sensor Networks Using Physically Unclonable Functions: A Case Study},
author = {Mario Barbareschi and Salvatore Barone and Alfonso Fezza and Erasmo La Montagna},
editor = {Ana C. R. Paiva and Ana Rosa Cavalli and Paula Ventura Martins and Ricardo Pérez-Castillo},
url = {https://link.springer.com/10.1007/978-3-030-85347-1_22},
doi = {10.1007/978-3-030-85347-1_22},
isbn = {978-3-030-85346-4 978-3-030-85347-1},
year = {2021},
date = {2021-01-01},
urldate = {2024-07-04},
booktitle = {Quality of Information and Communications Technology},
volume = {1439},
pages = {297–310},
publisher = {Springer International Publishing},
address = {Cham},
abstract = {The technological progress we witnessed in recent years has led to a pervasive usage of smart and embedded devices in many application domains. The monitoring of Power Delivery Networks (PDNs) is an example: the use of interconnected sensors makes it possible to detect faults and to dynamically adapt the network topology to isolate and compensate for them. In this paper we discuss how Fault-Detection, Isolation and Service Recovery (FDISR) for PDNs can be modeled according to the fog-computing paradigm, which distributes part of the computation among edge nodes and the cloud. In particular, we consider an FDISR application on Medium-Voltage PDNs (MV-PDNs) based on a Wireless Sensor Network (WSN) whose nodes make use of the Long Range (LoRa) technology to communicate with each other. Security concerns and the attack model of such application are discussed, then the use of a communication protocol based on the Physically Unclonable Functions (PUFs) mechanism is proposed to achieve both mutual authentication and confidentiality. Finally, an implementation of the proposal is presented and evaluated w.r.t. security concerns and communication overhead.},
note = {Series Title: Communications in Computer and Information Science},
keywords = {Dependable Systems, Distributed Systems},
pubstate = {published},
tppubtype = {inproceedings}
}
The technological progress we witnessed in recent years has led to a pervasive usage of smart and embedded devices in many application domains. The monitoring of Power Delivery Networks (PDNs) is an example: the use of interconnected sensors makes it possible to detect faults and to dynamically adapt the network topology to isolate and compensate for them. In this paper we discuss how Fault-Detection, Isolation and Service Recovery (FDISR) for PDNs can be modeled according to the fog-computing paradigm, which distributes part of the computation among edge nodes and the cloud. In particular, we consider an FDISR application on Medium-Voltage PDNs (MV-PDNs) based on a Wireless Sensor Network (WSN) whose nodes make use of the Long Range (LoRa) technology to communicate with each other. Security concerns and the attack model of such application are discussed, then the use of a communication protocol based on the Physically Unclonable Functions (PUFs) mechanism is proposed to achieve both mutual authentication and confidentiality. Finally, an implementation of the proposal is presented and evaluated w.r.t. security concerns and communication overhead.
Barone, Salvatore; Traiola, Marcello; Barbareschi, Mario; Bosio, Alberto
Multi-Objective Application-Driven Approximate Design Method Journal Article
In: IEEE Access, vol. 9, pp. 86975–86993, 2021, ISSN: 2169-3536.
Abstract | Links | BibTeX | Tags: Computer Aided Design Methodologies, Design-space Exploration
@article{barone_multi-objective_2021,
title = {Multi-Objective Application-Driven Approximate Design Method},
author = {Salvatore Barone and Marcello Traiola and Mario Barbareschi and Alberto Bosio},
doi = {10.1109/ACCESS.2021.3087858},
issn = {2169-3536},
year = {2021},
date = {2021-01-01},
journal = {IEEE Access},
volume = {9},
pages = {86975–86993},
abstract = {Approximate Computing (AxC) paradigm aims at designing computing systems that can satisfy the rising performance demands and improve the energy efficiency. AxC exploits the gap between the level of accuracy required by the users, and the actual precision provided by the computing system, for achieving diverse optimizations. Various AxC techniques have been proposed so far in the literature at different abstraction levels from hardware to software. These techniques have been successfully utilized and combined to realize approximate implementations of applications in various domains (e.g. data analytic, scientific computing, multimedia and signal processing, and machine learning). Unfortunately, state-of-the-art approximation methodologies focus on a single abstraction level, such as combining elementary components (e.g., arithmetic operations) which are firstly approximated using component-level metrics and then combined to provide a good trade-off between efficiency and accuracy at the application level. This hinders the possibility for designers to explore different approximation opportunities, optimized for different applications and implementation targets. Therefore, we designed and implemented E- $textbackslashmathbb IDEA$ , an automatic framework that provides an application-driven approximation approach to find the best approximate versions of a given application targeting different implementations (i.e., hardware and software). E- $textbackslashmathbb IDEA$ compounds 1) a source-to-source manipulation tool and 2) an evolutionary search engine to automatically realize approximate application variants and perform a Design-Space Exploration (DSE). The latter results in a set of non-dominate approximate solutions in terms of trade-off between accuracy and efficiency. Experimental results validate the effectiveness and the flexibility of the approach in generating optimized approximate implementations of different applications, by using different approximation techniques and different accuracy/error metrics and for different implementation targets.},
keywords = {Computer Aided Design Methodologies, Design-space Exploration},
pubstate = {published},
tppubtype = {article}
}
Approximate Computing (AxC) paradigm aims at designing computing systems that can satisfy the rising performance demands and improve the energy efficiency. AxC exploits the gap between the level of accuracy required by the users, and the actual precision provided by the computing system, for achieving diverse optimizations. Various AxC techniques have been proposed so far in the literature at different abstraction levels from hardware to software. These techniques have been successfully utilized and combined to realize approximate implementations of applications in various domains (e.g. data analytic, scientific computing, multimedia and signal processing, and machine learning). Unfortunately, state-of-the-art approximation methodologies focus on a single abstraction level, such as combining elementary components (e.g., arithmetic operations) which are firstly approximated using component-level metrics and then combined to provide a good trade-off between efficiency and accuracy at the application level. This hinders the possibility for designers to explore different approximation opportunities, optimized for different applications and implementation targets. Therefore, we designed and implemented E- $textbackslashmathbb IDEA$ , an automatic framework that provides an application-driven approximation approach to find the best approximate versions of a given application targeting different implementations (i.e., hardware and software). E- $textbackslashmathbb IDEA$ compounds 1) a source-to-source manipulation tool and 2) an evolutionary search engine to automatically realize approximate application variants and perform a Design-Space Exploration (DSE). The latter results in a set of non-dominate approximate solutions in terms of trade-off between accuracy and efficiency. Experimental results validate the effectiveness and the flexibility of the approach in generating optimized approximate implementations of different applications, by using different approximation techniques and different accuracy/error metrics and for different implementation targets.
Barbareschi, Mario; Barone, Salvatore; Fezza, Alfonso; Montagna, Erasmo La
Enforcing Mutual Authentication and Confidentiality in Wireless Sensor Networks Using Physically Unclonable Functions: A Case Study Proceedings Article
In: Paiva, Ana C. R.; Cavalli, Ana Rosa; Martins, Paula Ventura; Pérez-Castillo, Ricardo (Ed.): Quality of Information and Communications Technology, pp. 297–310, Springer International Publishing, Cham, 2021, ISBN: 978-3-030-85346-4 978-3-030-85347-1, (Series Title: Communications in Computer and Information Science).
Abstract | Links | BibTeX | Tags: Dependable Systems, Distributed Systems
@inproceedings{paiva_enforcing_2021,
title = {Enforcing Mutual Authentication and Confidentiality in Wireless Sensor Networks Using Physically Unclonable Functions: A Case Study},
author = {Mario Barbareschi and Salvatore Barone and Alfonso Fezza and Erasmo La Montagna},
editor = {Ana C. R. Paiva and Ana Rosa Cavalli and Paula Ventura Martins and Ricardo Pérez-Castillo},
url = {https://link.springer.com/10.1007/978-3-030-85347-1_22},
doi = {10.1007/978-3-030-85347-1_22},
isbn = {978-3-030-85346-4 978-3-030-85347-1},
year = {2021},
date = {2021-01-01},
urldate = {2024-07-04},
booktitle = {Quality of Information and Communications Technology},
volume = {1439},
pages = {297–310},
publisher = {Springer International Publishing},
address = {Cham},
abstract = {The technological progress we witnessed in recent years has led to a pervasive usage of smart and embedded devices in many application domains. The monitoring of Power Delivery Networks (PDNs) is an example: the use of interconnected sensors makes it possible to detect faults and to dynamically adapt the network topology to isolate and compensate for them. In this paper we discuss how Fault-Detection, Isolation and Service Recovery (FDISR) for PDNs can be modeled according to the fog-computing paradigm, which distributes part of the computation among edge nodes and the cloud. In particular, we consider an FDISR application on Medium-Voltage PDNs (MV-PDNs) based on a Wireless Sensor Network (WSN) whose nodes make use of the Long Range (LoRa) technology to communicate with each other. Security concerns and the attack model of such application are discussed, then the use of a communication protocol based on the Physically Unclonable Functions (PUFs) mechanism is proposed to achieve both mutual authentication and confidentiality. Finally, an implementation of the proposal is presented and evaluated w.r.t. security concerns and communication overhead.},
note = {Series Title: Communications in Computer and Information Science},
keywords = {Dependable Systems, Distributed Systems},
pubstate = {published},
tppubtype = {inproceedings}
}
The technological progress we witnessed in recent years has led to a pervasive usage of smart and embedded devices in many application domains. The monitoring of Power Delivery Networks (PDNs) is an example: the use of interconnected sensors makes it possible to detect faults and to dynamically adapt the network topology to isolate and compensate for them. In this paper we discuss how Fault-Detection, Isolation and Service Recovery (FDISR) for PDNs can be modeled according to the fog-computing paradigm, which distributes part of the computation among edge nodes and the cloud. In particular, we consider an FDISR application on Medium-Voltage PDNs (MV-PDNs) based on a Wireless Sensor Network (WSN) whose nodes make use of the Long Range (LoRa) technology to communicate with each other. Security concerns and the attack model of such application are discussed, then the use of a communication protocol based on the Physically Unclonable Functions (PUFs) mechanism is proposed to achieve both mutual authentication and confidentiality. Finally, an implementation of the proposal is presented and evaluated w.r.t. security concerns and communication overhead.
2019
Barbareschi, Mario; Barone, Salvatore; Mazzeo, Antonino; Mazzocca, Nicola
Efficient Reed-Muller Implementation for Fuzzy Extractor Schemes Proceedings Article
In: 2019 14th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS), pp. 1–2, 2019.
Abstract | Links | BibTeX | Tags: Error correction codes, Hardware
@inproceedings{barbareschiEfficientReedMullerImplementation2019,
title = {Efficient Reed-Muller Implementation for Fuzzy Extractor Schemes},
author = {Mario Barbareschi and Salvatore Barone and Antonino Mazzeo and Nicola Mazzocca},
doi = {10.1109/DTIS.2019.8735029},
year = {2019},
date = {2019-04-01},
booktitle = {2019 14th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)},
pages = {1–2},
abstract = {Nowadays, physical tampering and counterfeiting of electronic devices are still an important security problem and have a great impact on large-scale and distributed applications, such as Internet-of-Things. Physical Unclonable Functions (PUFs) have the potential to be a fundamental means to guarantee intrinsic hardware security, since they promise immunity against most of known attack models. However, inner nature of PUF circuits hinders a wider adoption since responses turn out to be noisy and not stable during time. To overcome this issue, most of PUF implementations require a fuzzy extraction scheme, able to recover responses stability by exploiting error correction codes (ECCs). In this paper, we propose a Reed-Muller (RM) ECC design, meant to be embedded into a fuzzy extractor, that can be efficiently configured in terms of area/delay constraints in order to get reliable responses from PUFs. We provide implementation details and experimental evidences of area/delay efficiency through syntheses on medium-range FPGA device.},
keywords = {Error correction codes, Hardware},
pubstate = {published},
tppubtype = {inproceedings}
}
Nowadays, physical tampering and counterfeiting of electronic devices are still an important security problem and have a great impact on large-scale and distributed applications, such as Internet-of-Things. Physical Unclonable Functions (PUFs) have the potential to be a fundamental means to guarantee intrinsic hardware security, since they promise immunity against most of known attack models. However, inner nature of PUF circuits hinders a wider adoption since responses turn out to be noisy and not stable during time. To overcome this issue, most of PUF implementations require a fuzzy extraction scheme, able to recover responses stability by exploiting error correction codes (ECCs). In this paper, we propose a Reed-Muller (RM) ECC design, meant to be embedded into a fuzzy extractor, that can be efficiently configured in terms of area/delay constraints in order to get reliable responses from PUFs. We provide implementation details and experimental evidences of area/delay efficiency through syntheses on medium-range FPGA device.
Barbareschi, Mario; Barone, Salvatore; Mazzeo, Antonino; Mazzocca, Nicola
Efficient Reed-Muller Implementation for Fuzzy Extractor Schemes Proceedings Article
In: 2019 14th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS), pp. 1–2, 2019.
Abstract | Links | BibTeX | Tags: Error correction codes, Hardware
@inproceedings{barbareschi_efficient_2019,
title = {Efficient Reed-Muller Implementation for Fuzzy Extractor Schemes},
author = {Mario Barbareschi and Salvatore Barone and Antonino Mazzeo and Nicola Mazzocca},
doi = {10.1109/DTIS.2019.8735029},
year = {2019},
date = {2019-04-01},
booktitle = {2019 14th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)},
pages = {1–2},
abstract = {Nowadays, physical tampering and counterfeiting of electronic devices are still an important security problem and have a great impact on large-scale and distributed applications, such as Internet-of-Things. Physical Unclonable Functions (PUFs) have the potential to be a fundamental means to guarantee intrinsic hardware security, since they promise immunity against most of known attack models. However, inner nature of PUF circuits hinders a wider adoption since responses turn out to be noisy and not stable during time. To overcome this issue, most of PUF implementations require a fuzzy extraction scheme, able to recover responses stability by exploiting error correction codes (ECCs). In this paper, we propose a Reed-Muller (RM) ECC design, meant to be embedded into a fuzzy extractor, that can be efficiently configured in terms of area/delay constraints in order to get reliable responses from PUFs. We provide implementation details and experimental evidences of area/delay efficiency through syntheses on medium-range FPGA device.},
keywords = {Error correction codes, Hardware},
pubstate = {published},
tppubtype = {inproceedings}
}
Nowadays, physical tampering and counterfeiting of electronic devices are still an important security problem and have a great impact on large-scale and distributed applications, such as Internet-of-Things. Physical Unclonable Functions (PUFs) have the potential to be a fundamental means to guarantee intrinsic hardware security, since they promise immunity against most of known attack models. However, inner nature of PUF circuits hinders a wider adoption since responses turn out to be noisy and not stable during time. To overcome this issue, most of PUF implementations require a fuzzy extraction scheme, able to recover responses stability by exploiting error correction codes (ECCs). In this paper, we propose a Reed-Muller (RM) ECC design, meant to be embedded into a fuzzy extractor, that can be efficiently configured in terms of area/delay constraints in order to get reliable responses from PUFs. We provide implementation details and experimental evidences of area/delay efficiency through syntheses on medium-range FPGA device.